event attribute not allowed on arrays

[michg]

The following code leads to invalid attribute reference:

library ieee;
use ieee.std_logic_1164.all;

entity test7 is
port (
clk_i : in std_logic_vector(7 downto 0);
o : out std_logic
);
end entity test7;

architecture rtl of test7 is
begin
process (clk_i(0))
begin
if (clk_i(0)'event and clk_i(0)='1') then
o <= '1';
end if;
end process;

end architecture rtl;

[nickg]

Fixed by b312d94

[michg]

Thanks a lot, the issue is fixed, I suceeded now to move to the elaboration stage. Unfortunately components are not allowed in elaboration (regress/comp1.vhd: instanciating components is not supported yet) and my complete
design is build up with components and not with entities..

[nickg]

Unfortunately that's not implemented yet. Hopefully I'll add it soon.

[michg]

That would be very helpful. A less important point: omiting outputs at instanciating is not allowed. That would be a nice option to reduce typing.

[nickg]

Should be able to leave outputs unconnected now

[nickg]

I've added some very basic support for component instantiation. Might be worth having another go?