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when trying to elaborate a simple assert never, I get unsupported error:
library ieee;
use ieee.std_logic_1164.all;
entity psl_assert_never is
end entity;
architecture tb of psl_assert_never is
signal clk : std_logic;
signal a : std_logic;
begin
-- psl default clock is rising_edge(clk);
-- psl asrt_1 : assert never
-- (a = '1')
-- report "This should not happen";
end architecture;
nvc -a --psl psl_assert_never.vhd -e psl_assert_never -r
** Fatal: cannot handle PSL kind P_NEVER in psl_fsm_new
> psl_assert_never.vhd:17
|
17 | -- psl asrt_1 : assert never
The text was updated successfully, but these errors were encountered:
Hi,
when trying to elaborate a simple
assert never
, I get unsupported error:The text was updated successfully, but these errors were encountered: