An open-source VHDL library for FPGA design.

Naming Conventions

• Signal names start with s_
• Variable names start with v_
• Shared variable names start with sv_
• Names of registered signals/variables end with _r
• Constant and generic names are all-uppercase
• Generic names start with G_
• Input port names start with i_
• Output port names start with o_
• Input/output port names start with io_
• Names of testbench entities start with tb_