- used to communicate data between 2 synchronous clock domains
- configurable FIFO depth and width
- logic for generating empty/full, overflow/underflow falgs
This is a short tabular description of the contents of each folder in the repo.
| Folder | Description |
|---|---|
| rtl/SystemVerilog | SV RTL implementation files |
| rtl/VHDL | VHDL RTL implementation files |
| cocotb_sim | Functional Verification with CoCoTB (Python-based) |
| pyuvm_sim | Functional Verification with pyUVM (Python impl. of UVM standard) |
| uvm_sim | Functional Verification with UVM (SV impl. of UVM standard) |
| verilator_sim | Functional Verification with Verilator (C++ based) |
| mcy_sim | Mutation Coverage Testing of Verilator tb, using YoysHQ/mcy |
| formal | Formal Verification using PSL properties and YoysHQ/sby |
This is the tree view of the strcture of the repo.
. ├── rtl │ ├── SystemVerilog │ │ └── SV files │ └── VHDL │ └── VHD files ├── cocotb_sim │ ├── Makefile │ └── python files ├── pyuvm_sim │ ├── Makefile │ └── python files ├── uvm_sim │ └── .zip file ├── verilator_sim │ ├── Makefile │ └── verilator tb ├── mcy_sim │ ├── Makefile, (modified) SV files, Verilator tb │ └── scripts └── formal ├── Makefile └── PSL properties file, scripts