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AES electronic codebook implementation and example #145
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[package] | ||
name = "ecb-demo" | ||
version = "0.0.1" | ||
edition = "2018" | ||
authors = [ "Thales Fragoso <thales.fragosoz@gmail.com>"] | ||
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[dependencies] | ||
cortex-m = "0.6.2" | ||
cortex-m-rt = "0.6.12" | ||
rtt-target = {version = "0.2.0", features = ["cortex-m"] } | ||
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nrf52810-hal = { path = "../../nrf52810-hal", features = ["rt"], optional = true } | ||
nrf52832-hal = { path = "../../nrf52832-hal", features = ["rt"], optional = true } | ||
nrf52840-hal = { path = "../../nrf52840-hal", features = ["rt"], optional = true } | ||
nrf52833-hal = { path = "../../nrf52833-hal", features = ["rt"], optional = true } | ||
nrf51-hal = { path = "../../nrf51-hal", features = ["rt"], optional = true} | ||
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[[bin]] | ||
name = "ecb-demo" | ||
doc = false | ||
test = false | ||
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[features] | ||
51 = ["nrf51-hal"] | ||
52810 = ["nrf52810-hal"] | ||
52832 = ["nrf52832-hal"] | ||
52840 = ["nrf52840-hal"] | ||
52833 = ["nrf52833-hal"] |
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[probe] | ||
# The index of the probe in the connected probe list. | ||
# probe_index = 0 | ||
# The protocol to be used for communicating with the target. | ||
protocol = "Swd" | ||
# The speed in kHz of the data link to the target. | ||
# speed = 1337 | ||
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[flashing] | ||
# Whether or not the target should be flashed. | ||
enabled = true | ||
# Whether or not the target should be halted after flashing. | ||
halt_afterwards = false | ||
# Whether or not bytes erased but not rewritten with data from the ELF | ||
# should be restored with their contents before erasing. | ||
restore_unwritten_bytes = false | ||
# The path where an SVG of the assembled flash layout should be written to. | ||
# flash_layout_output_path = "out.svg" | ||
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[general] | ||
# The chip name of the chip to be debugged. | ||
# chip = "nRF52832" | ||
# A list of chip descriptions to be loaded during runtime. | ||
chip_descriptions = [] | ||
# The default log level to be used. | ||
log_level = "Warn" | ||
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[rtt] | ||
# Whether or not an RTTUI should be opened after flashing. | ||
# This is exclusive and cannot be used with GDB at the moment. | ||
enabled = true | ||
# A list of channel associations to be displayed. If left empty, all channels are displayed. | ||
channels = [ | ||
# { up = 0, down = 0, name = "name" } | ||
] | ||
# The duration in ms for which the logger should retry to attach to RTT. | ||
timeout = 3000 | ||
# Whether timestamps in the RTTUI are enabled | ||
show_timestamps = true | ||
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[gdb] | ||
# Whether or not a GDB server should be opened after flashing. | ||
# This is exclusive and cannot be used with RTT at the moment. | ||
enabled = false | ||
# The connection string in host:port format wher the GDB server will open a socket. | ||
# gdb_connection_string | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Is it normal to check this file into git? There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Yes, this file is meant to be checked into git, assuming you/your users use cargo embed :) |
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# AES electronic codebook mode encryption demo | ||
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Choose the microcontroller with one of the following features: | ||
- 51 | ||
- 52810 | ||
- 52832 | ||
- 52840 | ||
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Also, if using `cargo-embed`, change the `chip` and `protocol` fields in [Embed.toml](Embed.toml). | ||
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This demo uses the [rtt-target](https://crates.io/crates/rtt-target) crate for communication. | ||
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If using `cargo-embed`, just run | ||
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```console | ||
$ cargo embed --release --features=52832 --target=thumbv7em-none-eabihf | ||
``` | ||
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Replace `52832` and `thumbv7em-none-eabihf` with the correct feature and target for your microcontroller. |
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#![no_std] | ||
#![no_main] | ||
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// Import the right HAL/PAC crate, depending on the target chip | ||
#[cfg(feature = "51")] | ||
pub use nrf51_hal as hal; | ||
#[cfg(feature = "52810")] | ||
pub use nrf52810_hal as hal; | ||
#[cfg(feature = "52832")] | ||
pub use nrf52832_hal as hal; | ||
#[cfg(feature = "52833")] | ||
pub use nrf52833_hal as hal; | ||
#[cfg(feature = "52840")] | ||
pub use nrf52840_hal as hal; | ||
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use { | ||
core::{ | ||
panic::PanicInfo, | ||
sync::atomic::{compiler_fence, Ordering}, | ||
}, | ||
cortex_m_rt::entry, | ||
hal::{Clocks, Ecb}, | ||
rtt_target::{rprint, rprintln, rtt_init_print}, | ||
}; | ||
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const MSG: [u8; 16] = *b"Message to encry"; | ||
const KEY: [u8; 16] = *b"aaaaaaaaaaaaaaaa"; | ||
const CIPHER_MSG: [u8; 16] = [ | ||
0xFE, 0xF1, 0x63, 0x82, 0xB4, 0x54, 0x6B, 0xE4, 0xEB, 0x9A, 0x5C, 0x0E, 0xB6, 0x0E, 0x49, 0x2F, | ||
]; | ||
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#[entry] | ||
fn main() -> ! { | ||
let p = hal::pac::Peripherals::take().unwrap(); | ||
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let _clocks = Clocks::new(p.CLOCK).enable_ext_hfosc(); | ||
rtt_init_print!(); | ||
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let mut ecb = Ecb::init(p.ECB); | ||
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loop { | ||
rprintln!("Starting Encryption\n"); | ||
rprintln!("Clear text: {}", core::str::from_utf8(&MSG[..]).unwrap()); | ||
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let cipher_text = ecb.encrypt_block(MSG, KEY).unwrap(); | ||
rprint!("Cipher Text: "); | ||
for number in cipher_text.iter() { | ||
rprint!("{:x} ", *number); | ||
} | ||
assert_eq!(cipher_text, CIPHER_MSG); | ||
rprintln!("\r\n Encryption Done\n"); | ||
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cortex_m::asm::delay(136_000_000); | ||
} | ||
} | ||
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#[inline(never)] | ||
#[panic_handler] | ||
fn panic(info: &PanicInfo) -> ! { | ||
rprintln!("{}", info); | ||
loop { | ||
compiler_fence(Ordering::SeqCst); | ||
} | ||
} |
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//! HAL interface to the AES electronic codebook mode encryption. | ||
//! | ||
//! The ECB encryption block supports 128 bit AES encryption (encryption only, not decryption). | ||
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use crate::target::ECB; | ||
use core::sync::atomic::{compiler_fence, Ordering}; | ||
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/// Error type to represent a sharing conflict during encryption. | ||
#[derive(Debug, Copy, Clone)] | ||
pub struct EncryptionError {} | ||
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/// A safe, blocking wrapper around the AES-ECB peripheral. | ||
/// | ||
/// It's really just blockwise AES and not an ECB stream cipher. Blocks can be | ||
/// encrypted by calling `crypt_block`. | ||
pub struct Ecb { | ||
regs: ECB, | ||
} | ||
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impl Ecb { | ||
/// Takes ownership of the `ECB` peripheral, returning a safe wrapper. | ||
pub fn init(regs: ECB) -> Self { | ||
// Disable all interrupts | ||
regs.intenclr | ||
.write(|w| w.endecb().clear().errorecb().clear()); | ||
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// NOTE(unsafe) 1 is a valid pattern to write to this register | ||
regs.tasks_stopecb.write(|w| unsafe { w.bits(1) }); | ||
Self { regs } | ||
} | ||
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/// Destroys `self`, giving the `ECB` peripheral back. | ||
pub fn into_inner(self) -> ECB { | ||
// Clear all events | ||
self.regs.events_endecb.reset(); | ||
self.regs.events_errorecb.reset(); | ||
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self.regs | ||
} | ||
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/// Blocking encryption. | ||
/// | ||
/// Encrypts a `block` with `key`. | ||
/// | ||
/// # Errors | ||
/// | ||
/// An error will be returned when the AES hardware raises an `ERRORECB` | ||
/// event. This can happen when an operation is started that shares the AES | ||
/// hardware resources with the AES ECB peripheral while an encryption | ||
/// operation is running. | ||
pub fn encrypt_block( | ||
&mut self, | ||
block: [u8; 16], | ||
key: [u8; 16], | ||
) -> Result<[u8; 16], EncryptionError> { | ||
#[repr(C)] | ||
struct EcbData { | ||
key: [u8; 16], | ||
clear_text: [u8; 16], | ||
cipher_text: [u8; 16], | ||
} | ||
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// We allocate the DMA'd buffer on the stack, which means that we must | ||
// not panic or return before the AES operation is finished. | ||
let mut buf = EcbData { | ||
key, | ||
clear_text: block, | ||
cipher_text: [0; 16], | ||
}; | ||
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// NOTE(unsafe) Any 32bits pattern is safe to write to this register | ||
self.regs | ||
.ecbdataptr | ||
.write(|w| unsafe { w.bits(&mut buf as *mut _ as u32) }); | ||
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// Clear all events | ||
self.regs.events_endecb.reset(); | ||
self.regs.events_errorecb.reset(); | ||
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// "Preceding reads and writes cannot be moved past subsequent writes." | ||
compiler_fence(Ordering::Release); | ||
// NOTE(unsafe) 1 is a valid pattern to write to this register | ||
self.regs.tasks_startecb.write(|w| unsafe { w.bits(1) }); | ||
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while self.regs.events_endecb.read().bits() == 0 | ||
&& self.regs.events_errorecb.read().bits() == 0 | ||
{} | ||
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// "Subsequent reads and writes cannot be moved ahead of preceding reads." | ||
compiler_fence(Ordering::Acquire); | ||
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if self.regs.events_errorecb.read().bits() == 1 { | ||
// It's ok to return here, the events will be cleared before the next encryption | ||
return Err(EncryptionError {}); | ||
} | ||
Ok(buf.cipher_text) | ||
} | ||
} |
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We now have support for the 52833 as well
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Also the new HAL needs to reexport this