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Linux SIMD tests

TST: Add CPU Dispatch test for RISC-V Vector Extenson. #3577

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TST: Add CPU Dispatch test for RISC-V Vector Extenson.

TST: Add CPU Dispatch test for RISC-V Vector Extenson. #3577

without avx512/avx2/fma3

without avx512/avx2/fma3
succeeded May 10, 2024 in 5m 55s