BUG, SIMD: Fix exp FP stack overflow when AVX512_SKX is enabled

[seiko2plus]

Don't count on the compiler for cast between mask and int registers.
On gcc7 with flags -march>=nocona -O3 can cause FP stack overflow
which may lead to putting NaN into certain HW/FP calculations.

For more details, please check the comments in #20356

closes #20356

[mattip]

I went through the use of overflow_mask, underflow_mask, invalid_mask, divide_by_zero_mask and it looks like you caught all the conversions to int. Cool.

[mattip]

Thanks @seiko2plus

[seiko2plus]

I went through the use of overflow_mask, underflow_mask, invalid_mask, divide_by_zero_mask and it looks like you caught all the conversions to int. Cool.

ops I didn't look deep enough, there're other areas:

numpy/numpy/core/src/umath/loops_exponent_log.dispatch.c.src

Lines 971 to 973 in 9959d3d

	glibc_mask = m1 & m2;
	if (glibc_mask != 0xFF) {

numpy/numpy/core/src/umath/loops_exponent_log.dispatch.c.src

Lines 1057 to 1058 in 9959d3d

	/* call glibc's log func when x around 1.0f */
	if (glibc_mask != 0) {

But my local tests passed, it seems that aggressive optimization didn't affect on them since they are inside the loop.
we need to get rid of any kind of raw SIMD, I will put this file into my highest priority.