Separate VM instruction set for unit control registers

[olofson]

As of now, the VM treats all registers the same way. To avoid unit callbacks for every single control register modification, and also to make duration info (provided by the next timing instruction executed) available to the callbacks, there is a piece of logic known as A2_regtracker, which keeps track of registers that have been written to, and does the actual callbacks all in one go when a timing instruction is issued.

NOTE: The 'set' instruction bypasses this and directly performs the control register callback, whereas any normal control register writes are actually performed by the next timing instruction!

In order to speed up register operations as well as enabling various higher level math optimizations (compound operation instructions etc), the A2_regtracker logic needs to be moved into the compiler, and the control register logic should be removed from the affected VM instructions. For this to work, we need to add timing instructions that can apply control register changes as specified by the compiler.

There is a hairy problem with this, though: Conditional code! It's perfectly possible to write code that only conditionally writes control registers before the next timing instruction. To deal with this, we'll have to either keep A2_regtracker for control registers, or have the compiler duplicate the code after the branches so it can issue different timing instructions. The latter sounds like big can of worms to open...