bl808: Add SoC and Ox64 devicetrees

Signed-off-by: Samuel Holland <samuel@sholland.org>

arch/riscv/dts/Makefile

@@ -1,6 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_BFLB_BL808) += bl808-ox64-d0.dtb
+dtb-$(CONFIG_TARGET_BFLB_BL808) += bl808-ox64-m0.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb

arch/riscv/dts/bl808-d0.dtsi

@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#define MCU_IRQ(n, f) (n)
+#define MM_IRQ(n, f) (16 + (n)) f
+
+#include "bl808.dtsi"
+
+/ {
+	cpus {
+		timebase-frequency = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "thead,c906", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			mmu-type = "riscv,sv39";
+			riscv,isa = "rv64imafdc";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	plic: interrupt-controller@e0000000 {
+		compatible = "thead,c900-plic";
+		reg = <0xe0000000 0x4000000>;
+		interrupts-extended = <&cpu0_intc 11>,
+				      <&cpu0_intc 9>;
+		interrupt-controller;
+		riscv,ndev = <82>;
+		#address-cells = <0>;
+		#interrupt-cells = <2>;
+	};
+
+	clint: timer@e4000000 {
+		compatible = "thead,c900-clint";
+		reg = <0xe4000000 0xc000>;
+		interrupts-extended = <&cpu0_intc 3>,
+				      <&cpu0_intc 7>;
+	};
+};
+
+&audio {
+	interrupt-parent = <&plic>;
+	interrupts = <MM_IRQ(64, IRQ_TYPE_LEVEL_HIGH)>;
+};
+
+&mcu_irq {
+	interrupt-parent = <&plic>;
+	interrupts = <MM_IRQ(65, IRQ_TYPE_LEVEL_HIGH)>;
+	status = "okay";
+};
+
+&mcu_peri {
+	interrupt-parent = <&mcu_irq>;
+};
+
+&mm_peri {
+	interrupt-parent = <&plic>;
+};
+
+&pds {
+	interrupt-parent = <&plic>;
+	interrupts = <MM_IRQ(66, IRQ_TYPE_LEVEL_HIGH)>;
+};

arch/riscv/dts/bl808-m0.dtsi

@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#define MCU_IRQ(n, f) (16 + (n)) f
+#define MM_IRQ(n, f) (n)
+
+#include "bl808.dtsi"
+
+/ {
+	cpus {
+		timebase-frequency = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "thead,e907", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-block-size = <32>;
+			d-cache-sets = <256>;
+			d-cache-size = <16384>;
+			i-cache-block-size = <32>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			riscv,isa = "rv32imafdc";
+		};
+	};
+
+	clint: timer@e0000000 {
+		compatible = "thead,e907-clint",
+			     "sifive,clint0";
+		reg = <0xe0000000 0x10000>;
+		interrupts-extended = <&clic 3 IRQ_TYPE_EDGE_RISING>,
+				      <&clic 7 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	clic: interrupt-controller@e0800000 {
+		compatible = "thead,e907-clic";
+		reg = <0xe0800000 0x5000>;
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <2>;
+	};
+};
+
+&mcu_peri {
+	interrupt-parent = <&clic>;
+};
+
+&mm_irq {
+	interrupt-parent = <&clic>;
+	interrupts = <MCU_IRQ(18, IRQ_TYPE_LEVEL_HIGH)>;
+	status = "okay";
+};
+
+&mm_peri {
+	interrupt-parent = <&mm_irq>;
+};

arch/riscv/dts/bl808-ox64-d0-u-boot.dtsi

@@ -0,0 +1,34 @@
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x50000000 0x4000000>;
+	};
+};
+
+&emac {
+	status = "okay";
+};
+
+&glb_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio {
+	u-boot,dm-pre-reloc;
+};
+
+&hbn_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&mm_glb {
+	u-boot,dm-pre-reloc;
+};
+
+&pds_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&uart3_pins {
+	u-boot,dm-pre-reloc;
+};

arch/riscv/dts/bl808-ox64-d0.dts

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+#include "bl808-d0.dtsi"
+#include "bl808-ox64.dtsi"
+
+/ {
+	compatible = "pine64,ox64", "bflb,bl808";
+	model = "Pine64 Ox64 (D0)";
+
+	aliases {
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial3:115200n8";
+	};
+};
+
+&uart3 {
+	status = "okay";
+};

arch/riscv/dts/bl808-ox64-m0-u-boot.dtsi

@@ -0,0 +1,30 @@
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x50000000 0x4000000>;
+	};
+};
+
+&emac {
+	status = "okay";
+};
+
+&glb_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio {
+	u-boot,dm-pre-reloc;
+};
+
+&hbn_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&pds_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0_pins {
+	u-boot,dm-pre-reloc;
+};

arch/riscv/dts/bl808-ox64-m0.dts

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+#include "bl808-m0.dtsi"
+#include "bl808-ox64.dtsi"
+
+/ {
+	compatible = "pine64,ox64", "bflb,bl808";
+	model = "Pine64 Ox64 (M0)";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};

arch/riscv/dts/bl808-ox64.dtsi

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&ext_xtal {
+	clock-frequency = <40000000>;
+};
+
+&gpio {
+	uart0_pins: uart0-pins {
+		pins = "GPIO14", "GPIO15";
+		function = "uart";
+	};
+
+	uart3_pins: uart3-pins {
+		pins = "GPIO16", "GPIO17";
+		function = "mm_uart";
+	};
+};
+
+&sdh {
+	status = "okay";
+};
+
+&sflash {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pins>;
+	pinctrl-names = "default";
+};
+
+&uart3 {
+	pinctrl-0 = <&uart3_pins>;
+	pinctrl-names = "default";
+};
+
+&usb {
+	dr_mode = "peripheral";
+	status = "okay";
+};