Merge pull request #1148 from strichmo/cv32e40p/merge_master_to_rel_18

Cv32e40p/merge master to rel 18
openhwgroup · Feb 2, 2022 · 819ca23 · 819ca23
2 parents 125314d + 3659606
commit 819ca23
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diff --git a/.gitignore b/.gitignore
@@ -36,7 +36,20 @@ stdout.txt
 .vscode
 cva6/tests/riscv-compliance/
 cva6/tests/riscv-tests/
-uvm/riscv-dv/
+cva6/sim/dv/
+cva6/sim/vcs_results
+cva6/sim/verilator_work
+cva6/sim/out_*
+cva6/sim/Mem_init.txt
+cva6/sim/trace*
+cva6/sim/simv*
+cva6/sim/ucli.key
+cva6/sim/.inter*
+cva6/sim/.vcs*
+cva6/sim/inter*
+cva6/sim/novas*
+cva6/sim/verdiLog
+cva6/sim/Verdi.ses*
 riviera_results/
 */vendor_lib/dpi_dasm_spike/
 */vendor_lib/verilab/svlib/

diff --git a/.metrics.json b/.metrics.json
@@ -1,7 +1,10 @@
 {
   "variables": {
     "LM_LICENSE_FILE": "2700@license-1",
-    "IMPERAS_QUEUE_LICENSE" : "1"
+    "IMPERAS_QUEUE_LICENSE" : "1",
+    "CV_SW_TOOLCHAIN" : "/opt/riscv",
+    "CV_SW_PREFIX" : "riscv32-unknown-elf-",
+    "CV_SIMULATOR" : "dsim"
   },
   "builds": {
     "list": [
@@ -20,50 +23,50 @@
       {
         "name":     "uvmt_cv32e40x",
         "image":    "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.2.0-7Dec2021",
-        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x_num_mhpmcounter_29",
         "image":    "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.2.0-7Dec2021",
-        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=num_mhpmcounter_29 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=num_mhpmcounter_29 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x_pma_1",
         "image":    "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.2.0-7Dec2021",
-        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_1 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_1 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x_pma_2",
         "image":    "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.2.0-7Dec2021",
-        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_2 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_2 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x_pma_3",
         "image":    "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.2.0-7Dec2021",
-        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_3 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_3 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x_pma_4",
         "image":    "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.2.0-7Dec2021",
-        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_4 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_4 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x_pma_5",
         "image":    "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.2.0-7Dec2021",
-        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_5 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_5 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x_compliance_build",
         "image":    "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.2.0-7Dec2021",
-        "cmd":      "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40s",
@@ -224,6 +227,7 @@
       "tests": {
         "resultsDir": "/mux-flow/build/results",
         "builds":    ["uvmt_cv32e40x", "uvmt_cv32e40x_pma_1", "uvmt_cv32e40x_pma_2" ],
+        "timeout":   "4h",
         "listCmd":   "/mux-flow/build/repo/bin/cv_regress --core=cv32e40x --file=cv32e40x_ci_check --metrics --outfile=/mux-flow/build/repo/cv32e40x_ci_check.json",
         "listFile":  "/mux-flow/build/repo/cv32e40x_ci_check.json"
       }

diff --git a/GitCheats.md b/GitCheats.md
@@ -87,6 +87,24 @@ $ git checkout master<br>
 $ git merge upstream/master<br>
 $ git push --set-upstream origin master<br>
 
+## Importing a new upstream branch onto your fork
+
+* Make sure you've pulled the new upstream branch into your local repo:
+* First, ensure your working tree is clean (commit/stash/revert any changes), then:
+
+$ git fetch upstream to retrieve the new upstream branch
+
+* Create and switch to a local version of the new upstream branch (newbranch):
+
+$ git checkout -b newbranch upstream/newbranch
+
+* When you're ready to push the new branch to origin:
+
+$ git push -u origin newbranch
+<br>
+The -u switch sets up tracking to the specified remote (in this example, origin).
+
+
 ## Using ssh (need to set-up ssh keys first)
 \# git remote set-url origin git@github.com:username/your-repository.git<br>
 $ git clone git@github.com:openhwgroup/core-v-verif.git master<br>

diff --git a/README.md b/README.md
@@ -22,6 +22,8 @@
 Functional verification project for the CORE-V family of RISC-V cores.
 
 ## NEWS UPDATES:
+**2021-07-15**: The verificaton environment for the [cv32e40s](https://github.com/openhwgroup/cv32e40s) is up and running.
+<br>
 **2021-03-23**: The verificaton environment for the [cv32e40x](https://github.com/openhwgroup/cv32e40x) is up and running.
 <br>
 **2020-12-16**: The [cv32e40p_v1.0.0](https://github.com/openhwgroup/core-v-verif/releases/tag/22dc5fc) of core-v-verif is released.
@@ -34,18 +36,22 @@ First, have a look at the [OpenHW Group's website](https://www.openhwgroup.org)
 <br>
 For first time users of CORE-V-VERIF, the **Quick Start Guide** in the [CORE-V-VERIF Verification Strategy](https://core-v-docs-verif-strat.readthedocs.io/en/latest/) is the best place to start.
 
+<!--
 ### Getting started with CV32E4\* cores
 If you want to run a simulation there are two options:
 1. To run the CORE testbench for the CV32E40P, go to `cv32e40p/sim/core` and read the README.
 2. To run any of the CV32E4\* UVM environment go to `mk/uvmt` and read the README.
+-->
 
 <!--
 #### CV32E40P coverage data
 The most recently published coverage report for the CV32E40P can be found [here](https://openhwgroup.github.io/core-v-verif/).
 -->
 
+<!--
 ### Getting started with CVA6
 To run CVA6 testbench, go to [cva6](cva6) directory and read the README.
+-->
 
 ## Directory Structure of this Repo
 ### bin
@@ -54,15 +60,11 @@ Various utilities for running tests and performing various verification-related
 ### core-v-cores
 Empty sub-directory into which the RTL from one or more of the [CORE-V-CORES](https://github.com/openhwgroup/core-v-cores) repositories is cloned.
 
-### cv32e40p
-Verification Environments, testbenches, testcases and simulation Makefiles for the CV32E40P core.
-
-### cva6
-Verification Environments, testbenches, testcases and simulation Makefiles for the CVA6 cores.
+### cv32e40p, cv32e40x, cv32e40s, cva6
+Core-specific verification code.
 
 ### docs
-Source for GitHub Pages.
-Contains a pointers to the [Verification Strategy document](https://core-v-docs-verif-strat.readthedocs.io/en/latest/), the [CORE-V-DOCS](https://github.com/openhwgroup/core-v-docs) repository, and available coverage reports.
+Sources for the Verification Strategy document, DV plans, coding style guidelines and available coverage reports.
 
 ### mk
 Common simulation Makefiles that support testbenches for all CORE-V cores.
@@ -79,7 +81,8 @@ We highly appreciate community contributions. You can get a sense of our current
 within a project are defined as [issues](https://github.com/openhwgroup/core-v-verif/issues) with a `task` label.
 <br><br>To ease our work of reviewing your contributions, please:
 
-* Review [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md).
+* Review [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md)
+and our [SV/UVM coding style guidelines](https://github.com/openhwgroup/core-v-verif/blob/master/docs/CodingStyleGuidelines.md).
 * Split large contributions into smaller commits addressing individual changes or bug fixes.
 Do not mix unrelated changes into the same commit!
 * Write meaningful commit messages.

diff --git a/bin/requirements.txt b/bin/requirements.txt
@@ -0,0 +1,11 @@
+bitstring==3.1.9
+constraint==0.4.1
+dv==1.0.10
+Jinja2==2.11.3
+junit_xml==1.9
+Pallets_Sphinx_Themes==2.0.2
+pandas==1.3.4
+pyvsc==0.6.3.1400856349
+setuptools==45.2.0
+sphinx_rtd_theme==1.0.0
+tabulate==0.8.9
diff --git a/cv32e40p/README.md b/cv32e40p/README.md
@@ -1,4 +1,7 @@
-# CV32: Verification Environment for the CV32 CORE-V processor core.
+# CV32E40P: Verification Environment for the CV32E40P CORE-V processor core.
+
+CV32E40P-specific SystemVerilog sources plus C and assembly test-program sources for the CV32E40P verification environment.
+Non-CV32E40P-specific verification components used in this verification environment are in `../lib` and `../vendor_lib`.
 
 ## Directories:
 - **bsp**:   the "board support package" for test-programs compiled/assembled/linked for the CV32E40P.  This BSP is used by both the `core` testbench and the `uvmt_cv32` UVM verification environment.
@@ -9,3 +12,5 @@
 
 There are README files in each directory with additional information.
 
+## Getting Started
+Check out the Quick Start Guide in the [CORE-V-VERIF Verification Strategy](https://core-v-docs-verif-strat.readthedocs.io/en/latest/).
diff --git a/cv32e40p/bsp/README.md b/cv32e40p/bsp/README.md
@@ -1,7 +1,7 @@
-Board Support Package (BSP) for CV32 Verification
-=================================================
+Board Support Package (BSP) for CV32E40P Verification
+=====================================================
 
-This BSP provides the code to support running programs on the CV32 verification
+This BSP provides the code to support running programs on the CV32E40P verification
 target. It performs initialization tasks (`crt0.S`), handles
 interrupts/exceptions (`vectors.S`, `handlers.S`), provides syscall
 implementations (`syscalls.c`) and includes a linker script (`link.ld`) to
@@ -138,7 +138,7 @@ The linker script defines the memory layout and controls the mapping of input
 sections from object files to output sections in the output binary.
 
 The `link.ld` script is based on the standard upstream RV32 linker script, with
-some changes required for CV32:
+some changes required for CV32E40P:
   * Memory layout is defined as follows:
     * `ram` start=0x0, length=4MB
     * `dbg` start=0x1A110800, length=2KB