CV32E40Pv2 Verification update

[XavierAubert]

Below are backlog updates for the last two months. I tried to organize everything to a more readable way, by topic, and to bring focus on important changes.

• Floating Point Instructions (Coverage, tests and fixes)

• A general rework of a dismissed PR ([cv32e40p] adding rv32f/zfinx functional coverage based on v2 testplans #1990) was added back into the environment (for details, see FPU FCOV XavierAubert/core-v-verif#95)

• After this rework, various updates have been made to improve coverage, fixes, analyzing redundant code (commits 03a57e1, 3dbad3a)

• By analyzing coverage, holes have been found and filled with new tests. First, mstatus.fs is covered by this new test (Added in Cv32e40p/bsm fp udpate testcases 1201 XavierAubert/core-v-verif#97, further improved/fixed in Added mstatus.fs write to initial state before fcsr clear. XavierAubert/core-v-verif#109)

• Illegal Instruction added for RV32FC Add illegal Instr contraint for RV32FC XavierAubert/core-v-verif#123

• HWLoop Instructions

• A vast majority of updates targetted on HWLoop are back-and-forth debugging to make sure all specific event and scenarios are correctly detected and general coverage improvements :

  • Enhance coverage to capture locations within hwloop for specific events XavierAubert/core-v-verif#96
  • Fix hwloop cvg issue for mix events with irq XavierAubert/core-v-verif#108
  • Fix hwloop cov model issues found in regression XavierAubert/core-v-verif#112
  • Improve to handle different trap scenarioes XavierAubert/core-v-verif#116
  • Fix issue when exception happen within debug mode XavierAubert/core-v-verif#119
  • 61b536f from Cv32e40p/bsm fix hwloop cvg n update tb XavierAubert/core-v-verif#120
  • Fix regress due to previous fixes XavierAubert/core-v-verif#122
  • 19edee3 from Cv32e40p/bsm update tb files 0112 XavierAubert/core-v-verif#128
  • d3e7cad from Cv32e40p/bsm update tb files 0119 XavierAubert/core-v-verif#130
  • Fix to handle corner case events - valid exception trap following by … XavierAubert/core-v-verif#138

• Interrupt & Debug

• Fix for Load and Stores instructions in debug program, and added PULP instructions generation inside debug program Cv32e40p/vja ww50 fixes XavierAubert/core-v-verif#103

• Random FP instructions streams added with interrupt & debug options enabled (commit 05d8227 from Cv32e40p/bsm update tb files 0109 XavierAubert/core-v-verif#124, frequency of debug request reduced afterwards for some tests in 069dc31 from Cv32e40p/bsm update tb files 0110 XavierAubert/core-v-verif#126)

• Flow/Regression updates and fixes

• A long-run issue inside our CI environment regarding UCDB merging and performance issues have been addressed during the past couple of months, experimenting a lot with Siemens tools options and tests timeout and their organization inside the regress lists (See Increase limit to fix regression issue XavierAubert/core-v-verif#100, Fix ucdb merge issue XavierAubert/core-v-verif#102, Fix ucdb merge issue which related to rtl path references XavierAubert/core-v-verif#107, c5cdd27, Disable trace logs generations in regression using vrun XavierAubert/core-v-verif#125, ee0a2c2, 93117b0)

• A new option has been added to regression generation, to allow a test to have a fixed seed (Added seed option for items in regress generation flow  XavierAubert/core-v-verif#127)

• Testbench updates and fixes

• Temporary workaround for GNU GCC issue Extensions state save and restore corev-gcc#36 in Temporary workaround for GNU GCC issue #36 XavierAubert/core-v-verif#113 and Added FP enable depending on configuration. XavierAubert/core-v-verif#129

• Toggle coverage collection removed 2f5ac42

• corev-dv generation fix regarding avail_regs that was causing issues (commit 13f5a60 from TB updates and improvements for ww48 XavierAubert/core-v-verif#98 and update randomize_avail_regs again to solve issues with compress instr… XavierAubert/core-v-verif#99

• commit 44647b9 inside PR TB updates and improvements for ww48 XavierAubert/core-v-verif#98 also addresses the following issue Clarify new illegal handler code for HWLOOPs #2286

• Prevent load & store from corrupting main code 56ba26f & d76e6b6 from Cv32e40p/bsm update tb files 0123 XavierAubert/core-v-verif#132

• Verification planning updates, tests additions, regression lists updates

• Additions to FPU Register / FP Instr test plan Add fp testcases information into verif plan XavierAubert/core-v-verif#75

• Removed the two cluster configurations from what is verified Updates for regress lists and v2 ci check XavierAubert/core-v-verif#104

• Added more debug tests for XPULP instructions, commit 36d1b29 in FCOV fixes XavierAubert/core-v-verif#111

• Added a new test to improve decoder coverage for CUSTOM opcodes illegal instructions (Added directed test for custom-[0-3] illegal instructions XavierAubert/core-v-verif#131, Added missing cases inside custom-3 opcodes (cv.sub) XavierAubert/core-v-verif#135, added 3 instructions that are not with OPCODE=custom XavierAubert/core-v-verif#136)

• Added new hwloop debug test 4361141 in Cv32e40p/bsm update tb files 0123 XavierAubert/core-v-verif#132

• Various test names & test options changes Changed regression running options for debug_test_boot_set test XavierAubert/core-v-verif#115, corrected testname XavierAubert/core-v-verif#118

[MikeOpenHWGroup]

Good work @XavierAubert (and not as much work as I feared - the test-program yamls are easy to review!). I have a few minor comments.

[MikeOpenHWGroup]

Thanks for the quick response to my comments. Approving and Merging.