Reference model #2432
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Reference model #2432
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torjeikenes
commented
May 14, 2024
cv32e40s/tests/programs/custom/custom_interrupt_test/custom_interrupt_test.h
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cv32e40s/tests/programs/custom/custom_interrupt_test/custom_interrupt_test.c
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torjeikenes
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May 15, 2024
cv32e40s/tests/programs/custom/custom_interrupt_test/custom_interrupt_test.c
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Conflicts: mk/uvmt/vsim.mk
Merge `cv32e40s/release`
silabs-robin
approved these changes
Jun 21, 2024
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This draft PR brings in some of my work implementing a reference model with the goal of verifying asynchronous events. The RM contains a core-specific pipeline shell, built around a core-independent ISS. The ISS is currently Spike from vendor/riscv/, with modifications done on another branch from master. This PR is therefore not currently functional and depends on #2427 before both branches can be merged. As discussed with @silabs-robin, I am submitting this PS as a draft in order to get feedback and track what changes need to be made.