migrate Verification Plans from core-v-docs to core-v-verif #582
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Break out ISA-level checks for instructions from core-specific vplans Signed-off-by: Steve Richmond <Steve.Richmond@silabs.com>
MikeOpenHWGroup
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May 5, 2021
JeanRochCoulon
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Feb 10, 2022
Static casts cause a compilation error with Verilator 4.109
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Break out ISA-level checks for instructions from core-specific vplans
Note that this is intentionally targetting the master branch as a hotfix. This will be followed up by a merge flow to propagate to appropriate core dev branches.
After this PR is approved and merged I will move to delete the plans from the core-v-docs master branch to avoid confusion and duplication.
Signed-off-by: Steve Richmond Steve.Richmond@silabs.com