Fix the encoding of alu instructions

[ChunyuLiao]

Spec:https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst

[jeremybennett]

@ChunyuLiao Thank you for this. Could you also post the lit results to this commit. Do we have any tests of the assembler included?

[ChunyuLiao]

~/corev-llvm-project/build/bin/llvm-lit ~/corev-llvm-project/llvm/test/MC/RISCV/corev/

-- Testing: 147 tests, 128 workers --
PASS: LLVM :: MC/RISCV/corev/alu/addrn-invalid.s (1 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/endi-invalid.s (2 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/sw-invalid.s (3 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addrnr.s (4 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/slet.s (5 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/sletu.s (6 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/beqimm-invalid.s (7 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/clip-invalid.s (8 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/macsrn.s (9 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lh-invalid.s (10 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subun.s (11 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/machhurn-invalid.s (12 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/invalid.s (13 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subn-invalid.s (14 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhsrn-invalid.s (15 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lhu-invalid.s (16 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lw-invalid.s (17 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/extbz-invalid.s (18 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/clipu.s (19 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addnr-invalid.s (20 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/max-invalid.s (21 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/fixups.s (22 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/macun-invalid.s (23 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/extbs.s (24 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/min-invalid.s (25 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/msu-invalid.s (26 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mac-invalid.s (27 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/sletu-invalid.s (28 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhurn-invalid.s (29 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulun.s (30 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addun.s (31 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhun-invalid.s (32 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addrnr-invalid.s (33 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/counti.s (34 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/clipu-invalid.s (35 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addurnr-invalid.s (36 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulsn-invalid.s (37 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subunr-invalid.s (38 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/abs-invalid.s (39 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/clipur-invalid.s (40 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subun-invalid.s (41 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/exthz-invalid.s (42 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/macsrn-invalid.s (43 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/macurn-invalid.s (44 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/exths-invalid.s (45 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subunr.s (46 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subrn-invalid.s (47 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subnr.s (48 of 147)
PASS: LLVM :: MC/RISCV/corev/alu-all-extensions.s (49 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhsrn.s (50 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/sh.s (51 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/minu.s (52 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/sw.s (53 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mac.s (54 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulun-invalid.s (55 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/setupi.s (56 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/machhsrn.s (57 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lb-invalid.s (58 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/invalid.s (59 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulsn.s (60 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/machhun.s (61 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addunr.s (62 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addunr-invalid.s (63 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/bneimm-invalid.s (64 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/slet-invalid.s (65 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/count.s (66 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/macsn-invalid.s (67 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/suburnr-invalid.s (68 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhs.s (69 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lw.s (70 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulurn-invalid.s (71 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulu-invalid.s (72 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addurnr.s (73 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/sb.s (74 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addn-invalid.s (75 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/extbs-invalid.s (76 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/starti.s (77 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/exths.s (78 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/machhurn.s (79 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/invalid.s (80 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/macsn.s (81 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/clipr.s (82 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/abs.s (83 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/clipur.s (84 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/clip.s (85 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulsrn.s (86 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/setupi-invalid.s (87 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/suburnr.s (88 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/sb-invalid.s (89 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/min.s (90 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/suburn-invalid.s (91 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addn.s (92 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lh.s (93 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/setup.s (94 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addrn.s (95 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/minu-invalid.s (96 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addnr.s (97 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/exthz.s (98 of 147)
PASS: LLVM :: MC/RISCV/corev/mac-all-extensions.s (99 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addurn.s (100 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/machhsn-invalid.s (101 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/extbz.s (102 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addun-invalid.s (103 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/endi.s (104 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/max.s (105 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulurn.s (106 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhun.s (107 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subn.s (108 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/maxu.s (109 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulu.s (110 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/suburn.s (111 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/counti-invalid.s (112 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/beqimm.s (113 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhurn.s (114 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/msu.s (115 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lbu.s (116 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/machhsn.s (117 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/muls.s (118 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/invalid.s (119 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/maxu-invalid.s (120 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulsrn-invalid.s (121 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/count-invalid.s (122 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/clipr-invalid.s (123 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subrnr.s (124 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lb.s (125 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhu.s (126 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/sh-invalid.s (127 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/bneimm.s (128 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhsn-invalid.s (129 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhu-invalid.s (130 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lhu.s (131 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subrn.s (132 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/muls-invalid.s (133 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/addurn-invalid.s (134 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/machhsrn-invalid.s (135 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/machhun-invalid.s (136 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/setup-invalid.s (137 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp-all-extensions.s (138 of 147)
PASS: LLVM :: MC/RISCV/corev/hwlp/starti-invalid.s (139 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/macurn.s (140 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhsn.s (141 of 147)
PASS: LLVM :: MC/RISCV/corev/mem/lbu-invalid.s (142 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subnr-invalid.s (143 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/mulhhs-invalid.s (144 of 147)
PASS: LLVM :: MC/RISCV/corev/mac/macun.s (145 of 147)
PASS: LLVM :: MC/RISCV/corev/mem-all-extensions.s (146 of 147)
PASS: LLVM :: MC/RISCV/corev/alu/subrnr-invalid.s (147 of 147)

Testing Time: 0.24s
Passed: 147

Also attached, ninja check:

---

---

Failed Tests (1):
LLVM :: CodeGen/RISCV/corev/alu.ll

Testing Time: 859.36s
Skipped : 92
Unsupported : 22318
Passed : 59812
Expectedly Failed: 85
Failed : 1

The assembler tests are in the .s file of pr, let me know if we need other tests

[ChunyuLiao]

ChunyuLiao@bf39d8f fix CodeGen/RISCV/corev/alu.ll

[jeremybennett]

This all looks clean to me. Great work. Even though there are a set of 85 lit failures, these are not to do with this patch. Therefore this patch can be approved.

[jeremybennett]

The only thing I might suggest is a richer commit message. This means those looking at this work in the future can get a better understanding of what this change relates to. I might for example have written in addition

The original encodings for the CORE-V ISA extensions were not compliant with the RISC-V standard. For version 2 of the CORE-V architecture, the ISA extension encodings were change to be compliant. This patch provides the encodings for the version 2 architecture. There is no need to preserver the version 1 encodings, since no CORE-V design implemented them.