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new parameters
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@davideschiavone
davideschiavone committed Jan 15, 2018
1 parent bfc2d6c commit 5fc6848
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Showing 5 changed files with 126 additions and 107 deletions.
5 changes: 0 additions & 5 deletions include/apu_core_package.sv
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Expand Up @@ -30,11 +30,6 @@ package apu_core_package;
// by default set to 0
parameter SHARED_INT_MULT = 0;

// CPU side / general params
parameter NARGS_CPU = 3;
parameter WOP_CPU = 6;
parameter NUSFLAGS_CPU = 5;
parameter NDSFLAGS_CPU = 15;
/////////////////////////////////////////////////////////////////////////////
// until here //
/////////////////////////////////////////////////////////////////////////////
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94 changes: 54 additions & 40 deletions riscv_core.sv
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Expand Up @@ -36,16 +36,20 @@ import riscv_defines::*;

module riscv_core
#(
parameter N_EXT_PERF_COUNTERS = 0,
parameter N_EXT_PERF_COUNTERS = 0,
parameter INSTR_RDATA_WIDTH = 32,
parameter PULP_SECURE = 0,
parameter PULP_CLUSTER = 1,
parameter FPU = 0,
parameter SHARED_FP = 0,
parameter SHARED_DSP_MULT = 0,
parameter SHARED_INT_DIV = 0,
parameter SHARED_FP_DIVSQRT = 0,
parameter WAPUTYPE = 0
parameter PULP_SECURE = 0,
parameter PULP_CLUSTER = 1,
parameter FPU = 0,
parameter SHARED_FP = 0,
parameter SHARED_DSP_MULT = 0,
parameter SHARED_INT_DIV = 0,
parameter SHARED_FP_DIVSQRT = 0,
parameter WAPUTYPE = 0,
parameter APU_NARGS_CPU = 3,
parameter APU_WOP_CPU = 6,
parameter APU_NDSFLAGS_CPU = 15,
parameter APU_NUSFLAGS_CPU = 5
)
(
// Clock and Reset
Expand Down Expand Up @@ -86,14 +90,14 @@ module riscv_core
output logic apu_master_ready_o,
input logic apu_master_gnt_i,
// request channel
output logic [31:0] apu_master_operands_o [NARGS_CPU-1:0],
output logic [WOP_CPU-1:0] apu_master_op_o,
output logic [WAPUTYPE-1:0] apu_master_type_o,
output logic [NDSFLAGS_CPU-1:0] apu_master_flags_o,
output logic [31:0] apu_master_operands_o [APU_NARGS_CPU-1:0],
output logic [APU_WOP_CPU-1:0] apu_master_op_o,
output logic [WAPUTYPE-1:0] apu_master_type_o,
output logic [APU_NDSFLAGS_CPU-1:0] apu_master_flags_o,
// response channel
input logic apu_master_valid_i,
input logic [31:0] apu_master_result_i,
input logic [NUSFLAGS_CPU-1:0] apu_master_flags_i,
input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i,

// Interrupt inputs
input logic irq_i, // level sensitive IR lines
Expand Down Expand Up @@ -201,26 +205,25 @@ module riscv_core


// APU
logic apu_en_ex;
logic [WAPUTYPE-1:0] apu_type_ex;
logic [NDSFLAGS_CPU-1:0] apu_flags_ex;

logic [WOP_CPU-1:0] apu_op_ex;
logic [1:0] apu_lat_ex;
logic [31:0] apu_operands_ex [NARGS_CPU-1:0];
logic [5:0] apu_waddr_ex;

logic [2:0][5:0] apu_read_regs;
logic [2:0] apu_read_regs_valid;
logic apu_read_dep;
logic [1:0][5:0] apu_write_regs;
logic [1:0] apu_write_regs_valid;
logic apu_write_dep;

logic perf_apu_type;
logic perf_apu_cont;
logic perf_apu_dep;
logic perf_apu_wb;
logic apu_en_ex;
logic [WAPUTYPE-1:0] apu_type_ex;
logic [APU_NDSFLAGS_CPU-1:0] apu_flags_ex;
logic [APU_WOP_CPU-1:0] apu_op_ex;
logic [1:0] apu_lat_ex;
logic [31:0] apu_operands_ex [APU_NARGS_CPU-1:0];
logic [5:0] apu_waddr_ex;

logic [2:0][5:0] apu_read_regs;
logic [2:0] apu_read_regs_valid;
logic apu_read_dep;
logic [1:0][5:0] apu_write_regs;
logic [1:0] apu_write_regs_valid;
logic apu_write_dep;

logic perf_apu_type;
logic perf_apu_cont;
logic perf_apu_dep;
logic perf_apu_wb;

// Register Write Control
logic [5:0] regfile_waddr_ex;
Expand Down Expand Up @@ -335,6 +338,10 @@ module riscv_core
//core busy signals
logic core_ctrl_firstfetch, core_busy_int, core_busy_q;

//Simchecker signal
logic is_interrupt;
assign is_interrupt = (pc_mux_id == PC_EXCEPTION) && (exc_pc_mux_id == EXC_PC_IRQ);

// APU master signals
generate
if ( SHARED_FP == 1) begin
Expand All @@ -360,7 +367,6 @@ module riscv_core
initial
begin
wait(rst_ni == 1'b1);

$sformat(fn, "apu_trace_core_%h_%h.log", cluster_id_i, core_id_i);
$display("[APU_TRACER] Output filename is: %s", fn);
apu_trace = $fopen(fn, "w");
Expand Down Expand Up @@ -529,7 +535,11 @@ module riscv_core
.SHARED_DSP_MULT ( SHARED_DSP_MULT ),
.SHARED_INT_DIV ( SHARED_INT_DIV ),
.SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ),
.WAPUTYPE ( WAPUTYPE )
.WAPUTYPE ( WAPUTYPE ),
.APU_NARGS_CPU ( APU_NARGS_CPU ),
.APU_WOP_CPU ( APU_WOP_CPU ),
.APU_NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ),
.APU_NUSFLAGS_CPU ( APU_NUSFLAGS_CPU )
)
id_stage_i
(
Expand Down Expand Up @@ -730,10 +740,14 @@ module riscv_core
/////////////////////////////////////////////////////
riscv_ex_stage
#(
.FPU ( FPU ),
.SHARED_FP ( SHARED_FP ),
.SHARED_DSP_MULT ( SHARED_DSP_MULT ),
.SHARED_INT_DIV ( SHARED_INT_DIV )
.FPU ( FPU ),
.SHARED_FP ( SHARED_FP ),
.SHARED_DSP_MULT ( SHARED_DSP_MULT ),
.SHARED_INT_DIV ( SHARED_INT_DIV ),
.APU_NARGS_CPU ( APU_NARGS_CPU ),
.APU_WOP_CPU ( APU_WOP_CPU ),
.APU_NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ),
.APU_NUSFLAGS_CPU ( APU_NUSFLAGS_CPU )
)
ex_stage_i
(
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5 changes: 3 additions & 2 deletions riscv_decoder.sv
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Expand Up @@ -37,7 +37,8 @@ module riscv_decoder
parameter SHARED_DSP_MULT = 0,
parameter SHARED_INT_DIV = 0,
parameter SHARED_FP_DIVSQRT = 0,
parameter WAPUTYPE = 0
parameter WAPUTYPE = 0,
parameter APU_WOP_CPU = 6
)
(
// singals running to/from controller
Expand Down Expand Up @@ -97,7 +98,7 @@ module riscv_decoder
// APU
output logic apu_en_o,
output logic [WAPUTYPE-1:0] apu_type_o,
output logic [WOP_CPU-1:0] apu_op_o,
output logic [APU_WOP_CPU-1:0] apu_op_o,
output logic [1:0] apu_lat_o,
output logic [WAPUTYPE-1:0] apu_flags_src_o,
output logic [2:0] fp_rnd_mode_o,
Expand Down
64 changes: 34 additions & 30 deletions riscv_ex_stage.sv
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Expand Up @@ -39,10 +39,14 @@ import riscv_defines::*;

module riscv_ex_stage
#(
parameter FPU = 0,
parameter SHARED_FP = 0,
parameter SHARED_DSP_MULT = 0,
parameter SHARED_INT_DIV = 0
parameter FPU = 0,
parameter SHARED_FP = 0,
parameter SHARED_DSP_MULT = 0,
parameter SHARED_INT_DIV = 0,
parameter APU_NARGS_CPU = 3,
parameter APU_WOP_CPU = 6,
parameter APU_NDSFLAGS_CPU = 15,
parameter APU_NUSFLAGS_CPU = 5
)
(
input logic clk,
Expand Down Expand Up @@ -77,41 +81,41 @@ module riscv_ex_stage
output logic mult_multicycle_o,

// FPU signals
input logic [C_CMD-1:0] fpu_op_i,
input logic [C_PC-1:0] fpu_prec_i,
output logic [C_FFLAG-1:0] fpu_fflags_o,
output logic fpu_fflags_we_o,
input logic [C_CMD-1:0] fpu_op_i,
input logic [C_PC-1:0] fpu_prec_i,
output logic [C_FFLAG-1:0] fpu_fflags_o,
output logic fpu_fflags_we_o,

// APU signals
input logic apu_en_i,
input logic [WOP_CPU-1:0] apu_op_i,
input logic [1:0] apu_lat_i,
input logic [31:0] apu_operands_i [NARGS_CPU-1:0],
input logic [5:0] apu_waddr_i,
input logic [NDSFLAGS_CPU-1:0] apu_flags_i,

input logic [2:0][5:0] apu_read_regs_i,
input logic [2:0] apu_read_regs_valid_i,
output logic apu_read_dep_o,
input logic [1:0][5:0] apu_write_regs_i,
input logic [1:0] apu_write_regs_valid_i,
output logic apu_write_dep_o,

output logic apu_perf_type_o,
output logic apu_perf_cont_o,
output logic apu_perf_wb_o,

output logic apu_busy_o,
output logic apu_ready_wb_o,
input logic apu_en_i,
input logic [APU_WOP_CPU-1:0] apu_op_i,
input logic [1:0] apu_lat_i,
input logic [31:0] apu_operands_i [APU_NARGS_CPU-1:0],
input logic [5:0] apu_waddr_i,
input logic [APU_NDSFLAGS_CPU-1:0] apu_flags_i,

input logic [2:0][5:0] apu_read_regs_i,
input logic [2:0] apu_read_regs_valid_i,
output logic apu_read_dep_o,
input logic [1:0][5:0] apu_write_regs_i,
input logic [1:0] apu_write_regs_valid_i,
output logic apu_write_dep_o,

output logic apu_perf_type_o,
output logic apu_perf_cont_o,
output logic apu_perf_wb_o,

output logic apu_busy_o,
output logic apu_ready_wb_o,

// apu-interconnect
// handshake signals
output logic apu_master_req_o,
output logic apu_master_ready_o,
input logic apu_master_gnt_i,
// request channel
output logic [31:0] apu_master_operands_o [NARGS_CPU-1:0],
output logic [WOP_CPU-1:0] apu_master_op_o,
output logic [31:0] apu_master_operands_o [APU_NARGS_CPU-1:0],
output logic [APU_WOP_CPU-1:0] apu_master_op_o,
// response channel
input logic apu_master_valid_i,
input logic [31:0] apu_master_result_i,
Expand Down
65 changes: 35 additions & 30 deletions riscv_id_stage.sv
View file
Expand Up @@ -39,16 +39,20 @@ import apu_core_package::*;

module riscv_id_stage
#(
parameter N_HWLP = 2,
parameter N_HWLP_BITS = $clog2(N_HWLP),
parameter PULP_SECURE = 0,
parameter FPU = 0,
parameter APU = 0,
parameter SHARED_FP = 0,
parameter SHARED_DSP_MULT = 0,
parameter SHARED_INT_DIV = 0,
parameter SHARED_FP_DIVSQRT = 0,
parameter WAPUTYPE = 0
parameter N_HWLP = 2,
parameter N_HWLP_BITS = $clog2(N_HWLP),
parameter PULP_SECURE = 0,
parameter FPU = 0,
parameter APU = 0,
parameter SHARED_FP = 0,
parameter SHARED_DSP_MULT = 0,
parameter SHARED_INT_DIV = 0,
parameter SHARED_FP_DIVSQRT = 0,
parameter WAPUTYPE = 0,
parameter APU_NARGS_CPU = 3,
parameter APU_WOP_CPU = 6,
parameter APU_NDSFLAGS_CPU = 15,
parameter APU_NUSFLAGS_CPU = 5
)
(
input logic clk,
Expand Down Expand Up @@ -139,13 +143,13 @@ module riscv_id_stage
output logic [C_CMD-1:0] fpu_op_ex_o,

// APU
output logic apu_en_ex_o,
output logic [WAPUTYPE-1:0] apu_type_ex_o,
output logic [WOP_CPU-1:0] apu_op_ex_o,
output logic [1:0] apu_lat_ex_o,
output logic [31:0] apu_operands_ex_o [NARGS_CPU-1:0],
output logic [NDSFLAGS_CPU-1:0] apu_flags_ex_o,
output logic [5:0] apu_waddr_ex_o,
output logic apu_en_ex_o,
output logic [WAPUTYPE-1:0] apu_type_ex_o,
output logic [APU_WOP_CPU-1:0] apu_op_ex_o,
output logic [1:0] apu_lat_ex_o,
output logic [31:0] apu_operands_ex_o [APU_NARGS_CPU-1:0],
output logic [APU_NDSFLAGS_CPU-1:0] apu_flags_ex_o,
output logic [5:0] apu_waddr_ex_o,

output logic [2:0][5:0] apu_read_regs_o,
output logic [2:0] apu_read_regs_valid_o,
Expand Down Expand Up @@ -341,13 +345,13 @@ module riscv_id_stage
logic [C_CMD-1:0] fpu_op;

// APU signals
logic apu_en;
logic [WAPUTYPE-1:0] apu_type;
logic [WOP_CPU-1:0] apu_op;
logic [1:0] apu_lat;
logic [31:0] apu_operands [NARGS_CPU-1:0];
logic [NDSFLAGS_CPU-1:0] apu_flags;
logic [5:0] apu_waddr;
logic apu_en;
logic [WAPUTYPE-1:0] apu_type;
logic [APU_WOP_CPU-1:0] apu_op;
logic [1:0] apu_lat;
logic [31:0] apu_operands [APU_NARGS_CPU-1:0];
logic [APU_NDSFLAGS_CPU-1:0] apu_flags;
logic [5:0] apu_waddr;

logic [2:0][5:0] apu_read_regs;
logic [2:0] apu_read_regs_valid;
Expand Down Expand Up @@ -795,11 +799,11 @@ module riscv_id_stage
generate
if (APU == 1) begin : apu_op_preparation

if (NARGS_CPU >= 1)
if (APU_NARGS_CPU >= 1)
assign apu_operands[0] = alu_operand_a;
if (NARGS_CPU >= 2)
if (APU_NARGS_CPU >= 2)
assign apu_operands[1] = alu_operand_b;
if (NARGS_CPU >= 3)
if (APU_NARGS_CPU >= 3)
assign apu_operands[2] = alu_operand_c;

// write reg
Expand Down Expand Up @@ -894,8 +898,8 @@ module riscv_id_stage
assign apu_write_regs_valid_o = apu_write_regs_valid;
end
else begin
for (genvar i=0;i<NARGS_CPU;i++)
assign apu_operands[i] = '0;
for (genvar i=0;i<APU_NARGS_CPU;i++)
assign apu_operands[i] = '0;
assign apu_waddr = '0;
assign apu_flags = '0;
assign apu_write_regs_o = '0;
Expand Down Expand Up @@ -974,7 +978,8 @@ module riscv_id_stage
.SHARED_DSP_MULT ( SHARED_DSP_MULT ),
.SHARED_INT_DIV ( SHARED_INT_DIV ),
.SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ),
.WAPUTYPE ( WAPUTYPE )
.WAPUTYPE ( WAPUTYPE ),
.APU_WOP_CPU ( APU_WOP_CPU )
)
decoder_i
(
Expand Down

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