update headers

include/apu_core_package.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at
@@ -48,27 +48,27 @@ package apu_core_package;
 
    // Int-Mult
    parameter APU_FLAGS_INT_MULT = 1;
-   
+
    // Int-div
-      
+
    // addsub
    parameter PIPE_REG_ADDSUB  = 1;
-         
+
    // mult
    parameter PIPE_REG_MULT = 1;
-   
+
    // casts
    parameter PIPE_REG_CAST = 1;
-   
+
    // mac
    parameter PIPE_REG_MAC = 2;
-   
+
    // div
    parameter PIPE_REG_DIV = 4;
-   
+
    // sqrt
    parameter PIPE_REG_SQRT = 5;
 
    // iter divsqrt
-   
+
 endpackage // apu_core_package

include/apu_macros.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

include/riscv_config.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

include/riscv_defines.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at
@@ -370,7 +370,7 @@ parameter C_FPU_FMADD_CMD     = 4'h8;
 parameter C_FPU_FMSUB_CMD     = 4'h9;
 parameter C_FPU_FNMADD_CMD    = 4'hA;
 parameter C_FPU_FNMSUB_CMD    = 4'hB;
-   
+
 parameter C_FFLAG             = 5;
 parameter C_RM                = 3;
 parameter C_RM_NEAREST        = 3'h0;

include/riscv_tracer_defines.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at
@@ -158,7 +158,7 @@ parameter INSTR_FMADD    =  { 5'b?,     2'b00, 10'b?,      3'b?,   5'b?, OPCODE_
 parameter INSTR_FMSUB    =  { 5'b?,     2'b00, 10'b?,      3'b?,   5'b?, OPCODE_OP_FMSUB  };
 parameter INSTR_FNMSUB   =  { 5'b?,     2'b00, 10'b?,      3'b?,   5'b?, OPCODE_OP_FNMSUB };
 parameter INSTR_FNMADD   =  { 5'b?,     2'b00, 10'b?,      3'b?,   5'b?, OPCODE_OP_FNMADD };
-   
+
 parameter INSTR_FADD     =  { 5'b00000, 2'b00, 10'b?,      3'b?,   5'b?, OPCODE_OP_FP };
 parameter INSTR_FSUB     =  { 5'b00001, 2'b00, 10'b?,      3'b?,   5'b?, OPCODE_OP_FP };
 parameter INSTR_FMUL     =  { 5'b00010, 2'b00, 10'b?,      3'b?,   5'b?, OPCODE_OP_FP };

riscv_L0_buffer.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_alu.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_alu_basic.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_alu_div.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_apu_disp.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at
@@ -76,8 +76,8 @@ module riscv_apu_disp (
   logic               req_accepted;
   logic               active;
   logic [1:0]         apu_lat;
-   
-   
+
+
   logic [2:0] read_deps_req,  read_deps_inflight,  read_deps_waiting;
   logic [1:0] write_deps_req, write_deps_inflight, write_deps_waiting;
   logic       read_dep_req,   read_dep_inflight,   read_dep_waiting;
@@ -90,7 +90,7 @@ module riscv_apu_disp (
   assign addr_req     = apu_waddr_i;
 
   assign req_accepted = valid_req & apu_master_gnt_i;
-   
+
   //
   // In-flight instructions
   //
@@ -106,7 +106,7 @@ module riscv_apu_disp (
       valid_waiting    <= 1'b0;
       addr_inflight    <= '0;
       addr_waiting     <= '0;
-    end else begin     
+    end else begin
        valid_inflight  <= valid_inflight_dn;
        valid_waiting   <= valid_waiting_dn;
        addr_inflight   <= addr_inflight_dn;
@@ -126,11 +126,11 @@ module riscv_apu_disp (
         if (valid_inflight & !(returned_inflight)) begin // we already have an inflight instruction!
            valid_waiting_dn = 1'b1;
            addr_waiting_dn  = addr_inflight;
-        end 
+        end
         if (returned_waiting) begin // we have received a new request and waiting goes out of the pipe but will be refilled
            valid_waiting_dn = 1'b1;
            addr_waiting_dn  = addr_inflight;
-        end 
+        end
      end // no new request
      else if (returned_inflight) begin // multicycle request has returned
         valid_inflight_dn   = '0;
@@ -143,7 +143,7 @@ module riscv_apu_disp (
         addr_waiting_dn     = '0;
      end
   end
-   
+
   //
   // Active type
   //
@@ -231,18 +231,18 @@ module riscv_apu_disp (
   // Performance counter signals
   assign perf_type_o = stall_type;
   assign perf_cont_o = stall_nack;
-   
+
   assign apu_multicycle_o  =  (apu_lat == 2'h3);
   assign apu_singlecycle_o = ~(valid_inflight | valid_waiting);
-   
+
   //
   // Assertions
   //
-  
+
 `ifndef VERILATOR
   assert property (
     @(posedge clk_i) (apu_master_valid_i) |-> (valid_req | valid_inflight | valid_waiting))
     else $warning("[APU Dispatcher] instruction returned while no instruction is in-flight");
 `endif
-   
+
 endmodule

riscv_compressed_decoder.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_controller.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_core.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_cs_registers.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_debug_unit.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_decoder.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_ex_stage.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at
@@ -81,15 +81,15 @@ module riscv_ex_stage
   input  logic [C_PC-1:0]            fpu_prec_i,
   output logic [C_FFLAG-1:0]         fpu_fflags_o,
   output logic                       fpu_fflags_we_o,
- 
+
   // APU signals
   input  logic                       apu_en_i,
   input  logic [WOP_CPU-1:0]         apu_op_i,
   input  logic [1:0]                 apu_lat_i,
   input  logic [31:0]                apu_operands_i [NARGS_CPU-1:0],
   input  logic [5:0]                 apu_waddr_i,
   input  logic [NDSFLAGS_CPU-1:0]    apu_flags_i,
- 
+
   input  logic [2:0][5:0]            apu_read_regs_i,
   input  logic [2:0]                 apu_read_regs_valid_i,
   output logic                       apu_read_dep_o,
@@ -100,10 +100,10 @@ module riscv_ex_stage
   output logic                       apu_perf_type_o,
   output logic                       apu_perf_cont_o,
   output logic                       apu_perf_wb_o,
- 
+
   output logic                       apu_busy_o,
   output logic                       apu_ready_wb_o,
- 
+
   // apu-interconnect
   // handshake signals
   output logic                       apu_master_req_o,
@@ -384,7 +384,7 @@ module riscv_ex_stage
          //  | |    | |    | |__| |  //
          //  |_|    |_|     \____/   //
          //////////////////////////////
-         
+
             fpu_private fpu_i
              (
               .clk_i          ( clk               ),
@@ -413,10 +413,10 @@ module riscv_ex_stage
             assign apu_master_operands_o[2] = '0;
             assign apu_master_op_o          = '0;
             assign apu_gnt                  = 1'b1;
-            
+
          end
 
-      end      
+      end
       else begin
          // default assignements for the case when no FPU/APU is attached.
          assign apu_master_req_o         = '0;

riscv_fetch_fifo.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_hwloop_controller.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_hwloop_regs.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_id_stage.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_if_stage.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_int_controller.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_load_store_unit.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_mult.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_prefetch_L0_buffer.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_prefetch_buffer.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_register_file.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_register_file_latch.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at

riscv_tracer.sv

@@ -1,4 +1,4 @@
-// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna.
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the “License”); you may not use this file except in
 // compliance with the License.  You may obtain a copy of the License at
@@ -65,7 +65,7 @@ module riscv_tracer
   input  logic        rs1_is_fp,
   input  logic        rs2_is_fp,
   input  logic        rs3_is_fp,
- 
+
   input  logic        ex_valid,
   input  logic [ 5:0] ex_reg_addr,
   input  logic        ex_reg_we,
@@ -217,7 +217,7 @@ module riscv_tracer
         str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2);
       end
     endfunction // printR3Instr
-     
+
     function void printF3Instr(input string mnemonic);
       begin
         regs_read.push_back('{rs1, rs1_value});
@@ -227,7 +227,7 @@ module riscv_tracer
         str = $sformatf("%-16s f%0d, f%0d, f%0d, f%0d", mnemonic, rd-32, rs1-32, rs2-32, rs4-32);
       end
     endfunction // printF3Instr
-    
+
     function void printF2Instr(input string mnemonic);
       begin
         regs_read.push_back('{rs1, rs1_value});
@@ -245,7 +245,7 @@ module riscv_tracer
         str = $sformatf("%-16s x%0d, f%0d, f%0d", mnemonic, rd, rs1-32, rs2-32);
       end
     endfunction // printF2IInstr
-     
+
     function void printFInstr(input string mnemonic);
       begin
         regs_read.push_back('{rs1, rs1_value});