Update documentation of instruction extensions for CV32E40P version 2. #760
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
| * ALU extensions, see :ref:`corev_alu`. | ||
| * Multiply-Accumulate extensions, see :ref:`corev_multiply_accumulate`. | ||
| * Single Instruction Multiple Data (aka SIMD) extensions, see :ref:`corev_simd`. | ||
| * Post-Incrementing load and stores, see :ref:`corev_load_store`, invoked in the tool chain with ``-march=xcvmem``. |
There was a problem hiding this comment.
Do we need to be more precise like -march=rv32i*_xcvmem
There was a problem hiding this comment.
That's a good suggestion. I'll make this change.
|
|
||
| Additionally the event load instruction (**cv.elw**) is supported by setting ``PULP_CLUSTER`` == 1, see :ref:`corev_event_load`. This is a separate ISA extension, invoked in the tool chain with ``-march=xcvelw``. | ||
|
|
||
| To use such instructions, you need to compile your SW with the CORE-V GCC or Clang/LLVM compiler. |
There was a problem hiding this comment.
Maybe we should specify starting from which version those instructions are supported by the toolchain, GCC and LLVM.
There was a problem hiding this comment.
A good suggestion. I'll make this change.
| @@ -1066,9 +1071,6 @@ performed. | |||
|
|
|||
| The custom SIMD extensions are only supported if ``PULP_XPULP`` == 1. | |||
|
|
|||
| **SIMD is not supported by the compiler of the tool chain** as it is not implementing auto-vectorization up to now. | |||
| But those instructions can be used either with builtins or even in assembly. | |||
|
|
|||
There was a problem hiding this comment.
I think we should keep this comment because it is still true.
There was a problem hiding this comment.
I will modify it. SIMD will be supported, but we won't have autovectization.
These changes particularly relate to how tool chain support is invoked using -march. We take the opportunity to remove caveats about ISA extensions not supported in the tool chain, since all are now supported in both GCC and Clang/LLVM. * docs/source/instruction_set_extensions.rst: Add -march tool chain invocations for each ISA extension and remove all caveats about compiler support. Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com>
jeremybennett
force-pushed
the
jpb-march-doc
branch
from
2e259b8
to
4c66da2
Compare
|
All comments by @pascalgouedo accepted and updated version force pushed. |
davideschiavone
added
the
Component:Doc
davideschiavone
approved these changes
Feb 6, 2023
davideschiavone
added a commit
that referenced
this pull request
Feb 14, 2023
* Correcting RFVI trace * Some clarifications about immediate in scalar replication on SIMD instructions. Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * Headers alignement. Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * Changed uvm_error in uvm_info in old tracer to avoid errors and header alignement. Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * Moved typedef definitions in rvfi_pkg and header alignement. Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * launched verible Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * Update documentation of instruction extensions for CV32E40P version 2. (#760) * Restored correct syntax * Update documentation of instruction extensions for CV32E40P version 2. These changes particularly relate to how tool chain support is invoked using -march. We take the opportunity to remove caveats about ISA extensions not supported in the tool chain, since all are now supported in both GCC and Clang/LLVM. * docs/source/instruction_set_extensions.rst: Add -march tool chain invocations for each ISA extension and remove all caveats about compiler support. Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com> --------- Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com> Co-authored-by: Davide Schiavone <davide@openhwgroup.org> Co-authored-by: pascalgouedo <pascal.gouedo@dolphin.fr> --------- Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com> Co-authored-by: Yoann Pruvost <yoann.pruvost@dolphin.fr> Co-authored-by: pascalgouedo <pascal.gouedo@dolphin.fr> Co-authored-by: Jeremy Bennett <jeremy.bennett@embecosm.com> Co-authored-by: Davide Schiavone <davide@openhwgroup.org>
davideschiavone
added a commit
that referenced
this pull request
Mar 7, 2023
* Restored correct syntax * Automatic PR dev->master (#766) * Correcting RFVI trace * Some clarifications about immediate in scalar replication on SIMD instructions. Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * Headers alignement. Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * Changed uvm_error in uvm_info in old tracer to avoid errors and header alignement. Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * Moved typedef definitions in rvfi_pkg and header alignement. Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * launched verible Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> * Update documentation of instruction extensions for CV32E40P version 2. (#760) * Restored correct syntax * Update documentation of instruction extensions for CV32E40P version 2. These changes particularly relate to how tool chain support is invoked using -march. We take the opportunity to remove caveats about ISA extensions not supported in the tool chain, since all are now supported in both GCC and Clang/LLVM. * docs/source/instruction_set_extensions.rst: Add -march tool chain invocations for each ISA extension and remove all caveats about compiler support. Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com> --------- Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com> Co-authored-by: Davide Schiavone <davide@openhwgroup.org> Co-authored-by: pascalgouedo <pascal.gouedo@dolphin.fr> --------- Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com> Co-authored-by: Yoann Pruvost <yoann.pruvost@dolphin.fr> Co-authored-by: pascalgouedo <pascal.gouedo@dolphin.fr> Co-authored-by: Jeremy Bennett <jeremy.bennett@embecosm.com> Co-authored-by: Davide Schiavone <davide@openhwgroup.org> * new block diagram (#14) --------- Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com> Co-authored-by: pascalgouedo <pascal.gouedo@dolphin.fr> Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> Co-authored-by: Yoann Pruvost <yoann.pruvost@dolphin.fr> Co-authored-by: Jeremy Bennett <jeremy.bennett@embecosm.com>
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Signed-off-by: Jeremy Bennett jeremy.bennett@embecosm.com