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Removed cv32e40s_align_check #460

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merged 2 commits into from May 25, 2023
Merged

Removed cv32e40s_align_check #460

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308188e
Removed cv32e40s_align_check and all its references.
silabs-oysteink May 25, 2023
43bd7ff
Removed unused signal and updated manifest file.
silabs-oysteink May 25, 2023
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5 changes: 2 additions & 3 deletions bhv/cv32e40s_rvfi.sv
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Expand Up @@ -113,7 +113,6 @@ module cv32e40s_rvfi
input logic csr_mnxti_in_wb_i,
input logic [31:0] wpt_match_wb_i,
input mpu_status_e mpu_status_wb_i,
input align_status_e align_status_wb_i,

// PC
input logic [31:0] branch_addr_n_i,
Expand Down Expand Up @@ -830,8 +829,8 @@ module cv32e40s_rvfi
// Indicate that a data transfer was blocked before reaching the bus.
logic mem_access_blocked_wb;
assign mem_access_blocked_wb = |wpt_match_wb_i ||
(mpu_status_wb_i != MPU_OK) ||
(align_status_wb_i != ALIGN_OK);
(mpu_status_wb_i != MPU_OK);


always_comb begin
rvfi_trap_next = '0;
Expand Down
1 change: 0 additions & 1 deletion bhv/cv32e40s_wrapper.sv
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Expand Up @@ -653,7 +653,6 @@ endgenerate
.mret_ptr_wb_i ( core_i.wb_stage_i.ex_wb_pipe_i.instr_meta.mret_ptr ),
.wpt_match_wb_i ( core_i.wb_stage_i.wpt_match_wb_o ),
.mpu_status_wb_i ( core_i.wb_stage_i.mpu_status_wb_o ),
.align_status_wb_i ( core_i.wb_stage_i.align_status_wb_o ),
.csr_mscratchcsw_in_wb_i ( core_i.cs_registers_i.mscratchcsw_in_wb ),
.csr_mscratchcswl_in_wb_i ( core_i.cs_registers_i.mscratchcswl_in_wb ),
.csr_mnxti_in_wb_i ( core_i.cs_registers_i.mnxti_in_wb ),
Expand Down
1 change: 0 additions & 1 deletion cv32e40s_manifest.flist
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Expand Up @@ -32,7 +32,6 @@ ${DESIGN_RTL_DIR}/include/cv32e40s_pkg.sv
${DESIGN_RTL_DIR}/cv32e40s_if_c_obi.sv
${DESIGN_RTL_DIR}/../bhv/include/cv32e40s_rvfi_pkg.sv
${DESIGN_RTL_DIR}/../bhv/cv32e40s_wrapper.sv
${DESIGN_RTL_DIR}/cv32e40s_align_check.sv
${DESIGN_RTL_DIR}/cv32e40s_dummy_instr.sv
${DESIGN_RTL_DIR}/cv32e40s_if_stage.sv
${DESIGN_RTL_DIR}/cv32e40s_csr.sv
Expand Down
183 changes: 0 additions & 183 deletions rtl/cv32e40s_align_check.sv
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This file was deleted.

2 changes: 0 additions & 2 deletions rtl/cv32e40s_controller.sv
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Expand Up @@ -69,7 +69,6 @@ module cv32e40s_controller import cv32e40s_pkg::*;
input ex_wb_pipe_t ex_wb_pipe_i,
input mpu_status_e mpu_status_wb_i, // MPU status (WB stage)
input logic [31:0] wpt_match_wb_i, // LSU watchpoint trigger in WB
input align_status_e align_status_wb_i, // Aligned status (atomics and mret pointers) in WB

// Last operation bits
input logic last_op_ex_i, // EX contains the last operation of an instruction
Expand Down Expand Up @@ -187,7 +186,6 @@ module cv32e40s_controller import cv32e40s_pkg::*;
.ex_wb_pipe_i ( ex_wb_pipe_i ),
.lsu_err_wb_i ( lsu_err_wb_i ),
.mpu_status_wb_i ( mpu_status_wb_i ),
.align_status_wb_i ( align_status_wb_i ),
.data_stall_wb_i ( data_stall_wb_i ),
.wb_ready_i ( wb_ready_i ),
.wb_valid_i ( wb_valid_i ),
Expand Down
11 changes: 4 additions & 7 deletions rtl/cv32e40s_controller_fsm.sv
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Expand Up @@ -71,7 +71,6 @@ module cv32e40s_controller_fsm import cv32e40s_pkg::*;
input logic last_op_wb_i, // WB stage contains the last operation of an instruction
input logic abort_op_wb_i, // WB stage contains an (to be) aborted instruction or sequence
input mpu_status_e mpu_status_wb_i, // MPU status (WB timing)
input align_status_e align_status_wb_i, // Aligned status (atomics) in WB
input logic [31:0] wpt_match_wb_i, // LSU watchpoint trigger (WB)


Expand Down Expand Up @@ -375,10 +374,9 @@ module cv32e40s_controller_fsm import cv32e40s_pkg::*;
!dcsr_i.ebreakm && !debug_mode_q) ||
(ex_wb_pipe_i.sys_en && ex_wb_pipe_i.sys_ebrk_insn && (ex_wb_pipe_i.priv_lvl == PRIV_LVL_U) &&
!dcsr_i.ebreaku && !debug_mode_q) ||
(mpu_status_wb_i != MPU_OK) ||
(align_status_wb_i != ALIGN_OK)) && ex_wb_pipe_i.instr_valid;
(mpu_status_wb_i != MPU_OK)) && ex_wb_pipe_i.instr_valid;

assign ctrl_fsm_o.exception_in_wb = exception_in_wb;
assign ctrl_fsm_o.exception_in_wb = exception_in_wb;

// Set exception cause
// For CLIC: Pointer fetches with PMA/PMP errors will get the exception code converted to LOAD_FAULT
Expand All @@ -395,9 +393,8 @@ module cv32e40s_controller_fsm import cv32e40s_pkg::*;
(ex_wb_pipe_i.sys_en && ex_wb_pipe_i.sys_ebrk_insn && (ex_wb_pipe_i.priv_lvl == PRIV_LVL_U) &&
!dcsr_i.ebreaku && !debug_mode_q) ? EXC_CAUSE_BREAKPOINT :
(mpu_status_wb_i == MPU_WR_FAULT) ? EXC_CAUSE_STORE_FAULT :
(mpu_status_wb_i == MPU_RE_FAULT) ? EXC_CAUSE_LOAD_FAULT :
(align_status_wb_i == ALIGN_WR_ERR) ? EXC_CAUSE_STORE_MISALIGNED :
EXC_CAUSE_LOAD_MISALIGNED;
EXC_CAUSE_LOAD_FAULT;


assign ctrl_fsm_o.exception_cause_wb = exception_cause_wb;

Expand Down
6 changes: 0 additions & 6 deletions rtl/cv32e40s_core.sv
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Expand Up @@ -264,7 +264,6 @@ module cv32e40s_core import cv32e40s_pkg::*;
logic lsu_last_op_ex;
mpu_status_e lsu_mpu_status_wb;
logic [31:0] lsu_wpt_match_wb;
align_status_e lsu_align_status_wb;
logic [31:0] lsu_rdata_wb;
lsu_err_wb_t lsu_err_wb;

Expand All @@ -287,7 +286,6 @@ module cv32e40s_core import cv32e40s_pkg::*;

logic [31:0] wpt_match_wb; // Sticky wpt_match from WB stage
mpu_status_e mpu_status_wb; // Sticky mpu_status from WB stage
align_status_e align_status_wb; // Sticky align_status from WB stage

// Stage ready signals
logic id_ready;
Expand Down Expand Up @@ -798,7 +796,6 @@ module cv32e40s_core import cv32e40s_pkg::*;

// Privilege level
.priv_lvl_lsu_i ( priv_lvl_lsu ),
.lsu_align_status_1_o ( lsu_align_status_wb),

// Valid/ready
.valid_0_i ( lsu_valid_ex ), // First LSU stage (EX)
Expand Down Expand Up @@ -840,7 +837,6 @@ module cv32e40s_core import cv32e40s_pkg::*;
.lsu_rdata_i ( lsu_rdata_wb ),
.lsu_mpu_status_i ( lsu_mpu_status_wb ),
.lsu_wpt_match_i ( lsu_wpt_match_wb ),
.lsu_align_status_i ( lsu_align_status_wb ),

// Write back to register file
.rf_we_wb_o ( rf_we_wb ),
Expand All @@ -861,7 +857,6 @@ module cv32e40s_core import cv32e40s_pkg::*;

.wpt_match_wb_o ( wpt_match_wb ),
.mpu_status_wb_o ( mpu_status_wb ),
.align_status_wb_o ( align_status_wb ),

// CSR/CLIC pointer inputs
.clic_pa_valid_i ( csr_clic_pa_valid ),
Expand Down Expand Up @@ -1025,7 +1020,6 @@ module cv32e40s_core import cv32e40s_pkg::*;
.ex_wb_pipe_i ( ex_wb_pipe ),
.mpu_status_wb_i ( mpu_status_wb ),
.wpt_match_wb_i ( wpt_match_wb ),
.align_status_wb_i ( align_status_wb ),

// last_op bits
.last_op_id_i ( last_op_id ),
Expand Down