CVXIF 1.0.0 #2340
CVXIF 1.0.0 #2340
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Gchauvon
requested review from
jquevremont,
JeanRochCoulon and
zarubaf
as code owners
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# Conflicts: # core/cva6.sv # core/ex_stage.sv # core/include/build_config_pkg.sv # core/issue_read_operands.sv # core/issue_stage.sv # verif/regress/smoke-tests.sh # verif/tests/testlist_cvxif.yaml # Conflicts: # core/cva6.sv # Conflicts: # verif/core-v-verif # Conflicts: # core/cva6.sv # core/id_stage.sv # core/include/build_config_pkg.sv # core/issue_read_operands.sv # core/issue_stage.sv # verif/core-v-verif
# Conflicts: # verif/env/uvme/cov/uvme_cva6_cov_model.sv # verif/env/uvme/uvme_cva6_cfg.sv # verif/env/uvme/uvme_cva6_env.sv # verif/env/uvme/uvme_cva6_pkg.flist # verif/env/uvme/uvme_cva6_vsqr.sv # verif/tb/uvmt/cva6_tb_wrapper.sv # verif/tb/uvmt/uvmt_cva6_dut_wrap.sv
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1 similar comment
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❌ failed run, report available here. |
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Hello, This PR introduced a new kind of warning in EDIT: mention that the warning occurs during synthesis |
Does this mean a combinatorial loop? |
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I guess so |
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I look into this. However gate simulation with timing works fine. That's why it was merged. |
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It is a misleading warning from DC_SHELL which is resolved in compile optimization. There are no combinatorial loop in the result netlist. |
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There are 4 loops looking like the one below : According to Synopsys's Solvnet this can happens during the GTECH representation of the design, it is then optimized away during compile. Synopsys recommends using |
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@cfuguet Can you give a look? This is in the HPDCache. |
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Hello ! Yes, I will take a look. But if the |
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Hello, I made a Synthesis and I did not found any timing loop warning in the reports. However, I needed to do some fixes in the RTL regarding "SUPERSCALAR" to get the CVA6 to synthesize. Hereafter the patch I applied. It is a workaround patch to get the synthesis to succeed (can you take a look @cathales ?) : --- a/core/ex_stage.sv
+++ b/core/ex_stage.sv
@@ -687,8 +687,8 @@ module ex_stage
vaddr_to_be_flushed <= '0;
// if the current instruction in EX_STAGE is a sfence.vma, in the next cycle no writes will happen
end else if ((~current_instruction_is_sfence_vma) && (~((fu_data_i[0].operation == SFENCE_VMA) && |csr_valid_i))) begin
- vaddr_to_be_flushed <= rs1_forwarding_i;
- asid_to_be_flushed <= rs2_forwarding_i[CVA6Cfg.ASID_WIDTH-1:0];
+ vaddr_to_be_flushed <= rs1_forwarding_i[0];
+ asid_to_be_flushed <= rs2_forwarding_i[0][CVA6Cfg.ASID_WIDTH-1:0];
end
end
endMy environment is the following for the synthesis: Design Compiler 2019.12-sp5-4 @Gchauvon, @jquevremont Can you tell me the configuration you are using for the synthesis to see if it is related to some specific parameter ? Thank you |
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Hello César, Thank you very much for the report, I will have a look at |
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Hello @cathales, Thank you. But anyway you should have an error with any configuration actually... The rs[12]_forwarding signals are 2-dimensional arrays, but in the code, only the second dimension is used, but with an index (ASID_WIDTH) that is not withing the range of the first dimension. Maybe you did not had the errors in your configurations because ASID_WIDTH is less than 2 in that configuration ? |
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A fix is available in #2384 |
Update CoreV-X-interface to its lastest version : release 1.0.0
It is not backward compatible with the old 0.2.0 implemented version.