CVXIF 1.0.0

.gitlab-ci.yml

@@ -398,7 +398,7 @@ generated_tests:
     - mv verif/sim/seedlist.yaml artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
-generated_xif_tests:
+.generated_xif_tests:
   extends:
     - .verif_test
   variables:
@@ -519,7 +519,7 @@ code_coverage-report:
   needs:
     - generated_tests
     - directed_isacov-tests
-    - generated_xif_tests
+#    - generated_xif_tests
     - csr_embedded_tests
   variables:
     DASHBOARD_JOB_TITLE: "Report merge coverage"

.gitlab-ci/expected_synth.yml

@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 162197
+  gates: 163431

Bender.yml

@@ -76,7 +76,6 @@ sources:
       - core/include/std_cache_pkg.sv
 
       # Extension Interface
-      - core/include/cvxif_pkg.sv
       - core/cvxif_example/include/cvxif_instr_pkg.sv
       - core/cvxif_fu.sv
       - core/cvxif_example/cvxif_example_coprocessor.sv

core/Flist.cva6

@@ -71,11 +71,14 @@ ${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
 ${CVA6_REPO_DIR}/core/include/build_config_pkg.sv
 
 //CVXIF
-${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
+${CVA6_REPO_DIR}/core/cvxif_compressed_if_driver.sv
+${CVA6_REPO_DIR}/core/cvxif_issue_register_commit_if_driver.sv
 ${CVA6_REPO_DIR}/core/cvxif_example/include/cvxif_instr_pkg.sv
 ${CVA6_REPO_DIR}/core/cvxif_fu.sv
 ${CVA6_REPO_DIR}/core/cvxif_example/cvxif_example_coprocessor.sv
 ${CVA6_REPO_DIR}/core/cvxif_example/instr_decoder.sv
+${CVA6_REPO_DIR}/core/cvxif_example/compressed_instr_decoder.sv
+${CVA6_REPO_DIR}/core/cvxif_example/copro_alu.sv
 
 // Common Cells
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv

core/Flist.cva6_gate

@@ -27,12 +27,11 @@ ${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
 ${CVA6_REPO_DIR}/core/include/build_config_pkg.sv
 
 //CVXIF
-${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
 ${CVA6_REPO_DIR}/core/cvxif_example/include/cvxif_instr_pkg.sv
-${CVA6_REPO_DIR}/core/cvxif_fu.sv
 ${CVA6_REPO_DIR}/core/cvxif_example/cvxif_example_coprocessor.sv
 ${CVA6_REPO_DIR}/core/cvxif_example/instr_decoder.sv
-${CVA6_REPO_DIR}/core/cva6_fifo_v3.sv
+${CVA6_REPO_DIR}/core/cvxif_example/compressed_instr_decoder.sv
+${CVA6_REPO_DIR}/core/cvxif_example/copro_alu.sv
 
 
 // Common Cells

core/cva6.sv

@@ -13,6 +13,7 @@
 // Description: CVA6 Top-level module
 
 `include "rvfi_types.svh"
+`include "cvxif_types.svh"
 
 module cva6
   import ariane_pkg::*;
@@ -272,8 +273,22 @@ module cva6
     //
     parameter type acc_cfg_t = logic,
     parameter acc_cfg_t AccCfg = '0,
-    parameter type cvxif_req_t = cvxif_pkg::cvxif_req_t,
-    parameter type cvxif_resp_t = cvxif_pkg::cvxif_resp_t
+    // CVXIF Types
+    parameter type readregflags_t = `READREGFLAGS_T(CVA6Cfg),
+    parameter type writeregflags_t = `WRITEREGFLAGS_T(CVA6Cfg),
+    parameter type id_t = `ID_T(CVA6Cfg),
+    parameter type hartid_t = `HARTID_T(CVA6Cfg),
+    parameter type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t),
+    parameter type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg),
+    parameter type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartit_t, id_t),
+    parameter type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t),
+    parameter type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t),
+    parameter type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t),
+    parameter type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t),
+    parameter type cvxif_req_t =
+    `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t),
+    parameter type cvxif_resp_t =
+    `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t)
 ) (
     // Subsystem Clock - SUBSYSTEM
     input logic clk_i,
@@ -343,8 +358,27 @@ module cva6
   logic             [CVA6Cfg.NrCommitPorts-1:0] commit_macro_ack;
 
   localparam NumPorts = 4;
-  cvxif_pkg::cvxif_req_t cvxif_req;
-  cvxif_pkg::cvxif_resp_t cvxif_resp;
+
+  // CVXIF
+  cvxif_req_t cvxif_req;
+  // CVXIF OUTPUTS
+  logic x_compressed_valid;
+  x_compressed_req_t x_compressed_req;
+  logic x_issue_valid;
+  x_issue_req_t x_issue_req;
+  logic x_register_valid;
+  x_register_t x_register;
+  logic x_commit_valid;
+  x_commit_t x_commit;
+  logic x_result_ready;
+  // CVXIF INPUTS
+  logic x_compressed_ready;
+  x_compressed_resp_t x_compressed_resp;
+  logic x_issue_ready;
+  x_issue_resp_t x_issue_resp;
+  logic x_register_ready;
+  logic x_result_valid;
+  x_result_t x_result;
 
   // --------------
   // PCGEN <-> CSR
@@ -437,9 +471,11 @@ module cva6
   logic x_valid_ex_id;
   exception_t x_exception_ex_id;
   logic x_we_ex_id;
+  logic [4:0] x_rd_ex_id;
   logic [CVA6Cfg.NrIssuePorts-1:0] x_issue_valid_id_ex;
   logic x_issue_ready_ex_id;
   logic [31:0] x_off_instr_id_ex;
+  logic x_transaction_rejected;
   // --------------
   // EX <-> COMMIT
   // --------------
@@ -633,7 +669,9 @@ module cva6
       .irq_ctrl_t(irq_ctrl_t),
       .scoreboard_entry_t(scoreboard_entry_t),
       .interrupts_t(interrupts_t),
-      .INTERRUPTS(INTERRUPTS)
+      .INTERRUPTS(INTERRUPTS),
+      .x_compressed_req_t(x_compressed_req_t),
+      .x_compressed_resp_t(x_compressed_resp_t)
   ) id_stage_i (
       .clk_i,
       .rst_ni,
@@ -652,20 +690,25 @@ module cva6
 
       .rvfi_is_compressed_o(rvfi_is_compressed),
 
-      .priv_lvl_i  (priv_lvl),
-      .v_i         (v),
-      .fs_i        (fs),
-      .vfs_i       (vfs),
-      .frm_i       (frm_csr_id_issue_ex),
-      .vs_i        (vs),
-      .irq_i       (irq_i),
-      .irq_ctrl_i  (irq_ctrl_csr_id),
-      .debug_mode_i(debug_mode),
-      .tvm_i       (tvm_csr_id),
-      .tw_i        (tw_csr_id),
-      .vtw_i       (vtw_csr_id),
-      .tsr_i       (tsr_csr_id),
-      .hu_i        (hu)
+      .priv_lvl_i        (priv_lvl),
+      .v_i               (v),
+      .fs_i              (fs),
+      .vfs_i             (vfs),
+      .frm_i             (frm_csr_id_issue_ex),
+      .vs_i              (vs),
+      .irq_i             (irq_i),
+      .irq_ctrl_i        (irq_ctrl_csr_id),
+      .debug_mode_i      (debug_mode),
+      .tvm_i             (tvm_csr_id),
+      .tw_i              (tw_csr_id),
+      .vtw_i             (vtw_csr_id),
+      .tsr_i             (tsr_csr_id),
+      .hu_i              (hu),
+      .hart_id_i         (hart_id_i),
+      .compressed_ready_i(x_compressed_ready),
+      .compressed_resp_i (x_compressed_resp),
+      .compressed_valid_o(x_compressed_valid),
+      .compressed_req_o  (x_compressed_req)
   );
 
   logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_ex_id;
@@ -693,16 +736,39 @@ module cva6
   assign ex_ex_ex_id[FPU_WB]    = fpu_exception_ex_id;
   assign wt_valid_ex_id[FPU_WB] = fpu_valid_ex_id;
 
+  always_comb begin : gen_cvxif_input_assignement
+    x_compressed_ready = cvxif_resp_i.compressed_ready;
+    x_compressed_resp  = cvxif_resp_i.compressed_resp;
+    x_issue_ready      = cvxif_resp_i.issue_ready;
+    x_issue_resp       = cvxif_resp_i.issue_resp;
+    x_register_ready   = cvxif_resp_i.register_ready;
+    x_result_valid     = cvxif_resp_i.result_valid;
+    x_result           = cvxif_resp_i.result;
+  end
   if (CVA6Cfg.CvxifEn) begin
+    always_comb begin : gen_cvxif_output_assignement
+      cvxif_req.compressed_valid = x_compressed_valid;
+      cvxif_req.compressed_req   = x_compressed_req;
+      cvxif_req.issue_valid      = x_issue_valid;
+      cvxif_req.issue_req        = x_issue_req;
+      cvxif_req.register_valid   = x_register_valid;
+      cvxif_req.register         = x_register;
+      cvxif_req.commit_valid     = x_commit_valid;
+      cvxif_req.commit           = x_commit;
+      cvxif_req.result_ready     = x_result_ready;
+    end
     assign trans_id_ex_id[X_WB] = x_trans_id_ex_id;
     assign wbdata_ex_id[X_WB]   = x_result_ex_id;
     assign ex_ex_ex_id[X_WB]    = x_exception_ex_id;
     assign wt_valid_ex_id[X_WB] = x_valid_ex_id;
   end else if (CVA6Cfg.EnableAccelerator) begin
+    assign cvxif_req = '0;
     assign trans_id_ex_id[ACC_WB] = acc_trans_id_ex_id;
     assign wbdata_ex_id[ACC_WB]   = acc_result_ex_id;
     assign ex_ex_ex_id[ACC_WB]    = acc_exception_ex_id;
     assign wt_valid_ex_id[ACC_WB] = acc_valid_ex_id;
+  end else begin
+    assign cvxif_req = '0;
   end
 
   if (CVA6Cfg.CvxifEn && CVA6Cfg.EnableAccelerator) begin : gen_err_xif_and_acc
@@ -718,63 +784,79 @@ module cva6
       .branchpredict_sbe_t(branchpredict_sbe_t),
       .exception_t(exception_t),
       .fu_data_t(fu_data_t),
-      .scoreboard_entry_t(scoreboard_entry_t)
+      .scoreboard_entry_t(scoreboard_entry_t),
+      .x_issue_req_t(x_issue_req_t),
+      .x_issue_resp_t(x_issue_resp_t),
+      .x_register_t(x_register_t),
+      .x_commit_t(x_commit_t)
   ) issue_stage_i (
       .clk_i,
       .rst_ni,
-      .sb_full_o             (sb_full),
-      .flush_unissued_instr_i(flush_unissued_instr_ctrl_id),
-      .flush_i               (flush_ctrl_id),
-      .stall_i               (stall_acc_id),
+      .sb_full_o               (sb_full),
+      .flush_unissued_instr_i  (flush_unissued_instr_ctrl_id),
+      .flush_i                 (flush_ctrl_id),
+      .stall_i                 (stall_acc_id),
       // ID Stage
-      .decoded_instr_i       (issue_entry_id_issue),
-      .orig_instr_i          (orig_instr_id_issue),
-      .decoded_instr_valid_i (issue_entry_valid_id_issue),
-      .is_ctrl_flow_i        (is_ctrl_fow_id_issue),
-      .decoded_instr_ack_o   (issue_instr_issue_id),
+      .decoded_instr_i         (issue_entry_id_issue),
+      .orig_instr_i            (orig_instr_id_issue),
+      .decoded_instr_valid_i   (issue_entry_valid_id_issue),
+      .is_ctrl_flow_i          (is_ctrl_fow_id_issue),
+      .decoded_instr_ack_o     (issue_instr_issue_id),
       // Functional Units
-      .rs1_forwarding_o      (rs1_forwarding_id_ex),
-      .rs2_forwarding_o      (rs2_forwarding_id_ex),
-      .fu_data_o             (fu_data_id_ex),
-      .pc_o                  (pc_id_ex),
-      .is_compressed_instr_o (is_compressed_instr_id_ex),
-      .tinst_o               (tinst_ex),
+      .rs1_forwarding_o        (rs1_forwarding_id_ex),
+      .rs2_forwarding_o        (rs2_forwarding_id_ex),
+      .fu_data_o               (fu_data_id_ex),
+      .pc_o                    (pc_id_ex),
+      .is_compressed_instr_o   (is_compressed_instr_id_ex),
+      .tinst_o                 (tinst_ex),
       // fixed latency unit ready
-      .flu_ready_i           (flu_ready_ex_id),
+      .flu_ready_i             (flu_ready_ex_id),
       // ALU
-      .alu_valid_o           (alu_valid_id_ex),
+      .alu_valid_o             (alu_valid_id_ex),
       // Branches and Jumps
-      .branch_valid_o        (branch_valid_id_ex),            // branch is valid
-      .branch_predict_o      (branch_predict_id_ex),          // branch predict to ex
-      .resolve_branch_i      (resolve_branch_ex_id),          // in order to resolve the branch
+      .branch_valid_o          (branch_valid_id_ex),            // branch is valid
+      .branch_predict_o        (branch_predict_id_ex),          // branch predict to ex
+      .resolve_branch_i        (resolve_branch_ex_id),          // in order to resolve the branch
       // LSU
-      .lsu_ready_i           (lsu_ready_ex_id),
-      .lsu_valid_o           (lsu_valid_id_ex),
+      .lsu_ready_i             (lsu_ready_ex_id),
+      .lsu_valid_o             (lsu_valid_id_ex),
       // Multiplier
-      .mult_valid_o          (mult_valid_id_ex),
+      .mult_valid_o            (mult_valid_id_ex),
       // FPU
-      .fpu_ready_i           (fpu_ready_ex_id),
-      .fpu_valid_o           (fpu_valid_id_ex),
-      .fpu_fmt_o             (fpu_fmt_id_ex),
-      .fpu_rm_o              (fpu_rm_id_ex),
+      .fpu_ready_i             (fpu_ready_ex_id),
+      .fpu_valid_o             (fpu_valid_id_ex),
+      .fpu_fmt_o               (fpu_fmt_id_ex),
+      .fpu_rm_o                (fpu_rm_id_ex),
       // ALU2
-      .alu2_valid_o          (alu2_valid_id_ex),
+      .alu2_valid_o            (alu2_valid_id_ex),
       // CSR
-      .csr_valid_o           (csr_valid_id_ex),
+      .csr_valid_o             (csr_valid_id_ex),
       // CVXIF
-      .x_issue_valid_o       (x_issue_valid_id_ex),
-      .x_issue_ready_i       (x_issue_ready_ex_id),
-      .x_off_instr_o         (x_off_instr_id_ex),
+      .xfu_valid_o             (x_issue_valid_id_ex),
+      .xfu_ready_i             (x_issue_ready_ex_id),
+      .x_off_instr_o           (x_off_instr_id_ex),
+      .hart_id_i               (hart_id_i),
+      .x_issue_ready_i         (x_issue_ready),
+      .x_issue_resp_i          (x_issue_resp),
+      .x_issue_valid_o         (x_issue_valid),
+      .x_issue_req_o           (x_issue_req),
+      .x_register_ready_i      (x_register_ready),
+      .x_register_valid_o      (x_register_valid),
+      .x_register_o            (x_register),
+      .x_commit_valid_o        (x_commit_valid),
+      .x_commit_o              (x_commit),
+      .x_transaction_rejected_o(x_transaction_rejected),
       // Accelerator
-      .issue_instr_o         (issue_instr_id_acc),
-      .issue_instr_hs_o      (issue_instr_hs_id_acc),
+      .issue_instr_o           (issue_instr_id_acc),
+      .issue_instr_hs_o        (issue_instr_hs_id_acc),
       // Commit
-      .resolved_branch_i     (resolved_branch),
-      .trans_id_i            (trans_id_ex_id),
-      .wbdata_i              (wbdata_ex_id),
-      .ex_ex_i               (ex_ex_ex_id),
-      .wt_valid_i            (wt_valid_ex_id),
-      .x_we_i                (x_we_ex_id),
+      .resolved_branch_i       (resolved_branch),
+      .trans_id_i              (trans_id_ex_id),
+      .wbdata_i                (wbdata_ex_id),
+      .ex_ex_i                 (ex_ex_ex_id),
+      .wt_valid_i              (wt_valid_ex_id),
+      .x_we_i                  (x_we_ex_id),
+      .x_rd_i                  (x_rd_ex_id),
 
       .waddr_i              (waddr_commit_id),
       .wdata_i              (wdata_commit_id),
@@ -806,7 +888,8 @@ module cva6
       .icache_arsp_t(icache_arsp_t),
       .icache_dreq_t(icache_dreq_t),
       .icache_drsp_t(icache_drsp_t),
-      .lsu_ctrl_t(lsu_ctrl_t)
+      .lsu_ctrl_t(lsu_ctrl_t),
+      .x_result_t(x_result_t)
   ) ex_stage_i (
       .clk_i(clk_i),
       .rst_ni(rst_ni),
@@ -877,13 +960,16 @@ module cva6
       .x_valid_i               (x_issue_valid_id_ex),
       .x_ready_o               (x_issue_ready_ex_id),
       .x_off_instr_i           (x_off_instr_id_ex),
+      .x_transaction_rejected_i(x_transaction_rejected),
       .x_trans_id_o            (x_trans_id_ex_id),
       .x_exception_o           (x_exception_ex_id),
       .x_result_o              (x_result_ex_id),
       .x_valid_o               (x_valid_ex_id),
       .x_we_o                  (x_we_ex_id),
-      .cvxif_req_o             (cvxif_req),
-      .cvxif_resp_i            (cvxif_resp),
+      .x_rd_o                  (x_rd_ex_id),
+      .x_result_valid_i        (x_result_valid),
+      .x_result_i              (x_result),
+      .x_result_ready_o        (x_result_ready),
       // Accelerator
       .acc_valid_i             (acc_valid_acc_ex),
       // Performance counters
@@ -1432,7 +1518,6 @@ module cva6
 
     // Feed through cvxif
     assign cvxif_req_o                = cvxif_req;
-    assign cvxif_resp                 = cvxif_resp_i;
   end : gen_no_accelerator
 
   // -------------------