remove branch predictor (#49)

* remove parameter BranchPredictor Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove references to the removed parameter(s) from examples Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from compliance verification Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from core lists Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from the example configurations Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove references to the removed parameter from documentation Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove related and dead code Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> --------- Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
openhwgroup · Jul 20, 2023 · 066ff47 · 066ff47
1 parent 7836dae
commit 066ff47
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diff --git a/cv32e20_manifest.flist b/cv32e20_manifest.flist
@@ -38,7 +38,6 @@ ${DESIGN_RTL_DIR}/cve2_tracer_pkg.sv
 ${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
 ${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
 ${DESIGN_RTL_DIR}/cve2_alu.sv
-${DESIGN_RTL_DIR}/cve2_branch_predict.sv
 ${DESIGN_RTL_DIR}/cve2_compressed_decoder.sv
 ${DESIGN_RTL_DIR}/cve2_controller.sv
 ${DESIGN_RTL_DIR}/cve2_cs_registers.sv

diff --git a/cve2_configs.yaml b/cve2_configs.yaml
@@ -13,7 +13,6 @@ small:
   RV32B                    : "cve2_pkg::RV32BNone"
   RegFile                  : "cve2_pkg::RegFileFF"
   WritebackStage           : 0
-  BranchPredictor          : 0
   PMPEnable                : 0
   PMPGranularity           : 0
   PMPNumRegions            : 4
@@ -25,7 +24,6 @@ opentitan:
   RV32B                    : "cve2_pkg::RV32BOTEarlGrey"
   RegFile                  : "cve2_pkg::RegFileFF"
   WritebackStage           : 1
-  BranchPredictor          : 0
   PMPEnable                : 1
   PMPGranularity           : 0
   PMPNumRegions            : 16
@@ -43,7 +41,6 @@ experimental-maxperf:
   RV32B                    : "cve2_pkg::RV32BNone"
   RegFile                  : "cve2_pkg::RegFileFF"
   WritebackStage           : 1
-  BranchPredictor          : 0
   PMPEnable                : 0
   PMPGranularity           : 0
   PMPNumRegions            : 4
@@ -55,7 +52,6 @@ experimental-maxperf-pmp:
   RV32B                    : "cve2_pkg::RV32BNone"
   RegFile                  : "cve2_pkg::RegFileFF"
   WritebackStage           : 1
-  BranchPredictor          : 0
   PMPEnable                : 1
   PMPGranularity           : 0
   PMPNumRegions            : 16
@@ -67,7 +63,6 @@ experimental-maxperf-pmp-bmbalanced:
   RV32B                    : "cve2_pkg::RV32BBalanced"
   RegFile                  : "cve2_pkg::RegFileFF"
   WritebackStage           : 1
-  BranchPredictor          : 0
   PMPEnable                : 1
   PMPGranularity           : 0
   PMPNumRegions            : 16
@@ -79,7 +74,6 @@ experimental-maxperf-pmp-bmfull:
   RV32B                    : "cve2_pkg::RV32BFull"
   RegFile                  : "cve2_pkg::RegFileFF"
   WritebackStage           : 1
-  BranchPredictor          : 0
   PMPEnable                : 1
   PMPGranularity           : 0
   PMPNumRegions            : 16
@@ -94,7 +88,6 @@ experimental-branch-predictor:
   RV32B                    : "cve2_pkg::RV32BNone"
   RegFile                  : "cve2_pkg::RegFileFF"
   WritebackStage           : 1
-  BranchPredictor          : 1
   PMPEnable                : 0
   PMPGranularity           : 0
   PMPNumRegions            : 4

diff --git a/cve2_top.core b/cve2_top.core
@@ -68,7 +68,6 @@ parameters:
     paramtype: vlogdefine
     description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
 
-
 targets:
   default: &default_target
     filesets:

diff --git a/cve2_top_tracing.core b/cve2_top_tracing.core
@@ -65,12 +65,6 @@ parameters:
     paramtype: vlogparam
     description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
 
-  BranchPredictor:
-    datatype: int
-    paramtype: vlogparam
-    default: 0
-    description: "Enables static branch prediction (EXPERIMENTAL)"
-
   SecureCVE2:
     datatype: int
     default: 0
@@ -121,7 +115,6 @@ targets:
       - ICache
       - ICacheECC
       - WritebackStage
-      - BranchPredictor
       - SecureCVE2
       - ICacheScramble
       - PMPEnable

diff --git a/doc/02_user/integration.rst b/doc/02_user/integration.rst
@@ -18,7 +18,6 @@ Instantiation Template
       .MHPMCounterWidth ( 40                               ),
       .RV32E            ( 0                                ),
       .RV32M            ( cve2_pkg::RV32MFast              ),
-      .BranchPrediction ( 0                                ),
       .RndCnstLfsrSeed  ( cve2_pkg::RndCnstLfsrSeedDefault ),
       .RndCnstLfsrPerm  ( cve2_pkg::RndCnstLfsrPermDefault ),
       .DmHaltAddr       ( 32'h1A110800                     ),
@@ -94,8 +93,6 @@ Parameters
 |                              |                     |            | "cve2_pkg::RV32MFast": 3-4 cycle multiplier, iterative divider        |
 |                              |                     |            | "cve2_pkg::RV32MSingleCycle": 1-2 cycle multiplier, iterative divider |
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
-| ``BranchPrediction``         | bit                 | 0          | *EXPERIMENTAL* Enable Static branch prediction                        |
-+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
 | ``DmHaltAddr``               | int                 | 0x1A110800 | Address to jump to when entering Debug Mode                           |
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
 | ``DmExceptionAddr``          | int                 | 0x1A110808 | Address to jump to when an exception occurs while in Debug Mode       |

diff --git a/doc/03_reference/coverage_plan.rst b/doc/03_reference/coverage_plan.rst
@@ -6,9 +6,6 @@ Coverage Plan
 .. note::
   Work to implement the functional coverage described in this plan is on-going and the plan itself is not yet complete.
 
-.. todo::
-  Branch prediction hasn't yet been considered, this will add more coverage points and alter some others
-
 Introduction
 ------------
 Ibex functional coverage is split into two major categories:

diff --git a/doc/03_reference/instruction_fetch.rst b/doc/03_reference/instruction_fetch.rst
@@ -21,16 +21,6 @@ A localparam ``DEPTH`` gives a configurable depth which is set to 3 by default.
 The top-level of the instruction fetch controls the prefetch buffer (in particular flushing it on branches/jumps/exception and beginning prefetching from the appropriate new PC) and supplies new instructions to the ID/EX stage along with their PC.
 Compressed instructions are expanded by the IF stage so the decoder can always deal with uncompressed instructions (the ID stage still receives the compressed instruction for placing into ``mtval`` on an illegal instruction exception).
 
-Branch Prediction
------------------
-
-Ibex can be configured to use static branch prediction by setting the ``BranchPrediction`` parameter to 1.
-This improves performance by predicting that any branch with a negative offset is taken and that any branch with a positive offset is not.
-When successful, the prediction removes a stall cycle from a taken branch.
-However, there is a mis-predict penalty if a branch is wrongly predicted to be taken.
-This penalty is at least one cycle, or at least two cycles if the instruction following the branch is uncompressed and not aligned.
-This feature is *EXPERIMENTAL* and its effects are not yet fully documented.
-
 Instruction-Side Memory Interface
 ---------------------------------
 

diff --git a/dv/riscv_compliance/cve2_riscv_compliance.core b/dv/riscv_compliance/cve2_riscv_compliance.core
@@ -59,12 +59,6 @@ parameters:
     paramtype: vlogparam
     description: "Enable ECC protection in instruction cache"
 
-  BranchPredictor:
-    datatype: int
-    paramtype: vlogparam
-    default: 0
-    description: "Enables static branch prediction (EXPERIMENTAL)"
-
   PMPEnable:
     datatype: int
     default: 0
@@ -108,7 +102,6 @@ targets:
       - RegFile
       - ICache
       - ICacheECC
-      - BranchPredictor
       - PMPEnable
       - PMPGranularity
       - PMPNumRegions

diff --git a/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv b/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv
@@ -24,7 +24,6 @@ module cve2_riscv_compliance (
   parameter cve2_pkg::regfile_e RegFile = cve2_pkg::RegFileFF;
   parameter bit ICache                  = 1'b0;
   parameter bit ICacheECC               = 1'b0;
-  parameter bit BranchPredictor         = 1'b0;
   parameter bit SecureIbex              = 1'b0;
   parameter bit ICacheScramble          = 1'b0;
 
@@ -121,7 +120,6 @@ module cve2_riscv_compliance (
       .RegFile         (RegFile         ),
       .ICache          (ICache          ),
       .ICacheECC       (ICacheECC       ),
-      .BranchPredictor (BranchPredictor ),
       .SecureIbex      (SecureIbex      ),
       .ICacheScramble  (ICacheScramble  ),
       .DmHaltAddr      (32'h00000000    ),

diff --git a/examples/simple_system/cve2_simple_system.core b/examples/simple_system/cve2_simple_system.core
@@ -66,12 +66,6 @@ parameters:
     paramtype: vlogparam
     description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]"
 
-  BranchPredictor:
-    datatype: int
-    paramtype: vlogparam
-    default: 0
-    description: "Enables static branch prediction (EXPERIMENTAL)"
-
   PMPEnable:
     datatype: int
     default: 0
@@ -104,7 +98,6 @@ targets:
       - ICacheScramble
       - ICacheECC
       - SecureIbex
-      - BranchPredictor
       - PMPEnable
       - PMPGranularity
       - PMPNumRegions

diff --git a/examples/simple_system/rtl/cve2_simple_system.sv b/examples/simple_system/rtl/cve2_simple_system.sv
@@ -46,7 +46,6 @@ module cve2_simple_system (
   parameter cve2_pkg::regfile_e RegFile                  = `RegFile;
   parameter bit                 ICache                   = 1'b0;
   parameter bit                 ICacheECC                = 1'b0;
-  parameter bit                 BranchPredictor          = 1'b0;
   parameter                     SRAMInitFile             = "";
 
   logic clk_sys = 1'b0, rst_sys_n;
@@ -173,7 +172,6 @@ module cve2_simple_system (
       .RegFile         ( RegFile         ),
       .ICache          ( ICache          ),
       .ICacheECC       ( ICacheECC       ),
-      .BranchPredictor ( BranchPredictor ),
       .DmHaltAddr      ( 32'h00100000    ),
       .DmExceptionAddr ( 32'h00100000    )
     ) u_top (

diff --git a/rtl/cve2_controller.sv b/rtl/cve2_controller.sv
@@ -11,7 +11,6 @@
 `include "dv_fcov_macros.svh"
 
 module cve2_controller #(
-  parameter bit BranchPredictor = 0
  ) (
   input  logic                  clk_i,
   input  logic                  rst_ni,
@@ -33,7 +32,6 @@ module cve2_controller #(
   input  logic [31:0]           instr_i,                 // uncompressed instr data for mtval
   input  logic [15:0]           instr_compressed_i,      // instr compressed data for mtval
   input  logic                  instr_is_compressed_i,   // instr is compressed
-  input  logic                  instr_bp_taken_i,        // instr was predicted taken branch
   input  logic                  instr_fetch_err_i,       // instr has error
   input  logic                  instr_fetch_err_plus2_i, // instr error is x32
   input  logic [31:0]           pc_id_i,                 // instr address
@@ -49,8 +47,6 @@ module cve2_controller #(
   output logic                  pc_set_o,                // jump to address set by pc_mux
   output cve2_pkg::pc_sel_e     pc_mux_o,                // IF stage fetch address selector
                                                          // (boot, normal, exception...)
-  output logic                  nt_branch_mispredict_o,  // Not-taken branch in ID/EX was
-                                                         // mispredicted (predicted taken)
   output cve2_pkg::exc_pc_sel_e exc_pc_mux_o,            // IF stage selector for exception PC
   output cve2_pkg::exc_cause_e  exc_cause_o,             // for IF stage, CSRs
 
@@ -62,7 +58,6 @@ module cve2_controller #(
   // jump/branch signals
   input  logic                  branch_set_i,            // branch set signal (branch definitely
                                                          // taken)
-  input  logic                  branch_not_set_i,        // branch is definitely not taken
   input  logic                  jump_set_i,              // jump taken set signal
 
   // interrupt signals
@@ -338,7 +333,6 @@ module cve2_controller #(
     // helping timing.
     pc_mux_o               = PC_BOOT;
     pc_set_o               = 1'b0;
-    nt_branch_mispredict_o = 1'b0;
 
     exc_pc_mux_o           = EXC_PC_IRQ;
     exc_cause_o            = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
@@ -458,21 +452,12 @@ module cve2_controller #(
         end
 
         if (branch_set_i || jump_set_i) begin
-          // Only set the PC if the branch predictor hasn't already done the branch for us
-          pc_set_o       = BranchPredictor ? ~instr_bp_taken_i : 1'b1;
+          pc_set_o       = 1'b1;
 
           perf_tbranch_o = branch_set_i;
           perf_jump_o    = jump_set_i;
         end
 
-        if (BranchPredictor) begin
-          if (instr_bp_taken_i & branch_not_set_i) begin
-            // If the instruction is a branch that was predicted to be taken but was not taken
-            // signal a mispredict.
-            nt_branch_mispredict_o = 1'b1;
-          end
-        end
-
         // If entering debug mode or handling an IRQ the core needs to wait until any instruction in
         // ID has finished executing. Stall IF during that time.
         if ((enter_debug_mode || handle_irq) && (stall || instr_valid_i)) begin
@@ -776,8 +761,6 @@ module cve2_controller #(
   // Assertions //
   ////////////////
 
-  `ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o |-> instr_valid_clear_o)
-
   // Selectors must be known/valid.
   `ASSERT(IbexCtrlStateValid, ctrl_fsm_cs inside {
       RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH,

diff --git a/rtl/cve2_core.sv b/rtl/cve2_core.sv
@@ -21,7 +21,6 @@ module cve2_core import cve2_pkg::*; #(
   parameter bit          RV32E             = 1'b0,
   parameter rv32m_e      RV32M             = RV32MFast,
   parameter rv32b_e      RV32B             = RV32BNone,
-  parameter bit          BranchPredictor   = 1'b0,
   parameter bit          DbgTriggerEn      = 1'b0,
   parameter int unsigned DbgHwBreakNum     = 1,
   parameter int unsigned DmHaltAddr        = 32'h1A110800,
@@ -119,7 +118,6 @@ module cve2_core import cve2_pkg::*; #(
   logic [15:0] instr_rdata_c_id;               // Compressed instruction sampled inside IF stage
   logic        instr_is_compressed_id;
   logic        instr_perf_count_id;
-  logic        instr_bp_taken_id;
   logic        instr_fetch_err;                // Bus error on instr fetch
   logic        instr_fetch_err_plus2;          // Instruction error is misaligned
   logic        illegal_c_insn_id;              // Illegal compressed instruction sent to ID stage
@@ -132,8 +130,6 @@ module cve2_core import cve2_pkg::*; #(
   logic        instr_first_cycle_id;
   logic        instr_valid_clear;
   logic        pc_set;
-  logic        nt_branch_mispredict;
-  logic [31:0] nt_branch_addr;
   pc_sel_e     pc_mux_id;                      // Mux selector for next PC
   exc_pc_sel_e exc_pc_mux_id;                  // Mux selector for exception PC
   exc_cause_e  exc_cause;                      // Exception cause
@@ -290,8 +286,7 @@ module cve2_core import cve2_pkg::*; #(
 
   cve2_if_stage #(
     .DmHaltAddr       (DmHaltAddr),
-    .DmExceptionAddr  (DmExceptionAddr),
-    .BranchPredictor  (BranchPredictor)
+    .DmExceptionAddr  (DmExceptionAddr)
   ) if_stage_i (
     .clk_i (clk_i),
     .rst_ni(rst_ni),
@@ -314,7 +309,6 @@ module cve2_core import cve2_pkg::*; #(
     .instr_rdata_alu_id_o    (instr_rdata_alu_id),
     .instr_rdata_c_id_o      (instr_rdata_c_id),
     .instr_is_compressed_id_o(instr_is_compressed_id),
-    .instr_bp_taken_o        (instr_bp_taken_id),
     .instr_fetch_err_o       (instr_fetch_err),
     .instr_fetch_err_plus2_o (instr_fetch_err_plus2),
     .illegal_c_insn_id_o     (illegal_c_insn_id),
@@ -327,13 +321,11 @@ module cve2_core import cve2_pkg::*; #(
     .instr_valid_clear_i   (instr_valid_clear),
     .pc_set_i              (pc_set),
     .pc_mux_i              (pc_mux_id),
-    .nt_branch_mispredict_i(nt_branch_mispredict),
     .exc_pc_mux_i          (exc_pc_mux_id),
     .exc_cause             (exc_cause),
 
     // branch targets
     .branch_target_ex_i(branch_target_ex),
-    .nt_branch_addr_i  (nt_branch_addr),
 
     // CSRs
     .csr_mepc_i      (csr_mepc),  // exception return address
@@ -361,8 +353,7 @@ module cve2_core import cve2_pkg::*; #(
   cve2_id_stage #(
     .RV32E          (RV32E),
     .RV32M          (RV32M),
-    .RV32B          (RV32B),
-    .BranchPredictor(BranchPredictor)
+    .RV32B          (RV32B)
   ) id_stage_i (
     .clk_i (clk_i),
     .rst_ni(rst_ni),
@@ -378,7 +369,6 @@ module cve2_core import cve2_pkg::*; #(
     .instr_rdata_alu_i    (instr_rdata_alu_id),
     .instr_rdata_c_i      (instr_rdata_c_id),
     .instr_is_compressed_i(instr_is_compressed_id),
-    .instr_bp_taken_i     (instr_bp_taken_id),
 
     // Jumps and branches
     .branch_decision_i(branch_decision),
@@ -390,8 +380,6 @@ module cve2_core import cve2_pkg::*; #(
     .instr_req_o           (instr_req_int),
     .pc_set_o              (pc_set),
     .pc_mux_o              (pc_mux_id),
-    .nt_branch_mispredict_o(nt_branch_mispredict),
-    .nt_branch_addr_o      (nt_branch_addr),
     .exc_pc_mux_o          (exc_pc_mux_id),
     .exc_cause_o           (exc_cause),