remove branch predictor

[christian-herber-nxp]

No description provided.

[christian-herber-nxp]

@davideschiavone : Could you please review?

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Module-level begin-end blocks are not LRM-valid syntax. [Style: floating-begin-end-blocks] [module-begin-block]

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Module-level begin-end blocks are not LRM-valid syntax. [Style: floating-begin-end-blocks] [module-begin-block]

[davideschiavone]

this signal is always 0, shall we just remove it from the cve2_controller and wherever it is used in the id_stage etc?

[szbieg]

Redundant signals were pruned.

[davideschiavone]

similarly to the previous comment, shall we just remove this signal and its leaf?

[davideschiavone]

can you @szbieg merge in again the main branch (I made some fixes for verilator)

Also let's removed unused/undeclered signals (or declare them if you use them) as:

I copy here the Verilator errors

ERROR: %Warning-IMPLICIT: ../../../rtl/cve2_if_stage.sv:261:10: Signal definition not found, creating implicitly: 'if_instr_valid'
                                                       : ... Suggested alternative: 'if_instr_err'
  261 |   assign if_instr_valid = fetch_valid;
      |          ^~~~~~~~~~~~~~
                   ... For warning description see https://verilator.org/warn/IMPLICIT?v=4.210
                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
%Warning-IMPLICIT: ../../../rtl/cve2_if_stage.sv:263:10: Signal definition not found, creating implicitly: 'if_instr_addr'
                                                       : ... Suggested alternative: 'if_instr_err'
  263 |   assign if_instr_addr  = fetch_addr;
      |          ^~~~~~~~~~~~~
%Warning-IMPLICIT: ../../../rtl/cve2_if_stage.sv:264:10: Signal definition not found, creating implicitly: 'if_instr_bus_err'
                                                       : ... Suggested alternative: 'if_instr_pmp_err'
  264 |   assign if_instr_bus_err = fetch_err;
      |          ^~~~~~~~~~~~~~~~
%Warning-WIDTH: ../../../rtl/cve2_if_stage.sv:263:25: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'fetch_addr' generates 32 bits.
                                                    : ... In instance cve2_top.u_cve2_core.if_stage_i
  263 |   assign if_instr_addr  = fetch_addr;
      |                         ^
%Warning-UNUSED: ../../../rtl/cve2_if_stage.sv:98:22: Bits of signal are not used: 'if_instr_rdata'[31:16]
                                                    : ... In instance cve2_top.u_cve2_core.if_stage_i
   98 |   logic       [31:0] if_instr_rdata;
      |                      ^~~~~~~~~~~~~~
%Warning-UNUSED: ../../../rtl/cve2_if_stage.sv:261:10: Signal is not used: 'if_instr_valid'
                                                     : ... In instance cve2_top.u_cve2_core.if_stage_i
  261 |   assign if_instr_valid = fetch_valid;
      |          ^~~~~~~~~~~~~~
%Warning-UNUSED: ../../../rtl/cve2_if_stage.sv:263:10: Signal is not used: 'if_instr_addr'
                                                     : ... In instance cve2_top.u_cve2_core.if_stage_i
  263 |   assign if_instr_addr  = fetch_addr;
      |          ^~~~~~~~~~~~~
%Warning-UNUSED: ../../../rtl/cve2_if_stage.sv:264:10: Signal is not used: 'if_instr_bus_err'
                                                     : ... In instance cve2_top.u_cve2_core.if_stage_i
  264 |   assign if_instr_bus_err = fetch_err;
      |          ^~~~~~~~~~~~~~~~
%Warning-UNUSED: ../../../rtl/cve2_controller.sv:62:33: Signal is not used: 'branch_not_set_i'
                                                      : ... In instance cve2_top.u_cve2_core.id_stage_i.controller_i
   62 |   input  logic                  branch_not_set_i,         
      |                                 ^~~~~~~~~~~~~~~~