Skip to content

Commit

Permalink
Remove related and dead code
Browse files Browse the repository at this point in the history 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
  • Loading branch information
@szbieg
szbieg committed Feb 23, 2023
1 parent b0ad956 commit edf92ee
Show file tree
Hide file tree
Showing 6 changed files with 21 additions and 93 deletions.
1 change: 0 additions & 1 deletion cv32e20_manifest.flist
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,6 @@ ${DESIGN_RTL_DIR}/cve2_tracer_pkg.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
${DESIGN_RTL_DIR}/cve2_alu.sv
${DESIGN_RTL_DIR}/cve2_branch_predict.sv
${DESIGN_RTL_DIR}/cve2_compressed_decoder.sv
${DESIGN_RTL_DIR}/cve2_controller.sv
${DESIGN_RTL_DIR}/cve2_cs_registers.sv
Expand Down
6 changes: 0 additions & 6 deletions rtl/cve2_controller.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,6 @@ module cve2_controller #(
input logic [31:0] instr_i, // uncompressed instr data for mtval
input logic [15:0] instr_compressed_i, // instr compressed data for mtval
input logic instr_is_compressed_i, // instr is compressed
input logic instr_bp_taken_i, // instr was predicted taken branch
input logic instr_fetch_err_i, // instr has error
input logic instr_fetch_err_plus2_i, // instr error is x32
input logic [31:0] pc_id_i, // instr address
Expand All @@ -48,8 +47,6 @@ module cve2_controller #(
output logic pc_set_o, // jump to address set by pc_mux
output cve2_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
// (boot, normal, exception...)
output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was
// mispredicted (predicted taken)
output cve2_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
output cve2_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs

Expand Down Expand Up @@ -380,7 +377,6 @@ module cve2_controller #(
// helping timing.
pc_mux_o = PC_BOOT;
pc_set_o = 1'b0;
nt_branch_mispredict_o = 1'b0;

exc_pc_mux_o = EXC_PC_IRQ;
exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
Expand Down Expand Up @@ -823,8 +819,6 @@ module cve2_controller #(
// Assertions //
////////////////

`ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o |-> instr_valid_clear_o)

// Selectors must be known/valid.
`ASSERT(IbexCtrlStateValid, ctrl_fsm_cs inside {
RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH,
Expand Down
9 changes: 0 additions & 9 deletions rtl/cve2_core.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -160,7 +160,6 @@ module cve2_core import cve2_pkg::*; #(
logic [15:0] instr_rdata_c_id; // Compressed instruction sampled inside IF stage
logic instr_is_compressed_id;
logic instr_perf_count_id;
logic instr_bp_taken_id;
logic instr_fetch_err; // Bus error on instr fetch
logic instr_fetch_err_plus2; // Instruction error is misaligned
logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage
Expand All @@ -185,8 +184,6 @@ module cve2_core import cve2_pkg::*; #(
logic instr_first_cycle_id;
logic instr_valid_clear;
logic pc_set;
logic nt_branch_mispredict;
logic [31:0] nt_branch_addr;
pc_sel_e pc_mux_id; // Mux selector for next PC
exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC
exc_cause_e exc_cause; // Exception cause
Expand Down Expand Up @@ -403,7 +400,6 @@ module cve2_core import cve2_pkg::*; #(
.instr_rdata_alu_id_o (instr_rdata_alu_id),
.instr_rdata_c_id_o (instr_rdata_c_id),
.instr_is_compressed_id_o(instr_is_compressed_id),
.instr_bp_taken_o (instr_bp_taken_id),
.instr_fetch_err_o (instr_fetch_err),
.instr_fetch_err_plus2_o (instr_fetch_err_plus2),
.illegal_c_insn_id_o (illegal_c_insn_id),
Expand All @@ -417,7 +413,6 @@ module cve2_core import cve2_pkg::*; #(
.instr_valid_clear_i (instr_valid_clear),
.pc_set_i (pc_set),
.pc_mux_i (pc_mux_id),
.nt_branch_mispredict_i(nt_branch_mispredict),
.exc_pc_mux_i (exc_pc_mux_id),
.exc_cause (exc_cause),
.dummy_instr_en_i (dummy_instr_en),
Expand All @@ -430,7 +425,6 @@ module cve2_core import cve2_pkg::*; #(

// branch targets
.branch_target_ex_i(branch_target_ex),
.nt_branch_addr_i (nt_branch_addr),

// CSRs
.csr_mepc_i (csr_mepc), // exception return address
Expand Down Expand Up @@ -494,7 +488,6 @@ module cve2_core import cve2_pkg::*; #(
.instr_rdata_alu_i (instr_rdata_alu_id),
.instr_rdata_c_i (instr_rdata_c_id),
.instr_is_compressed_i(instr_is_compressed_id),
.instr_bp_taken_i (instr_bp_taken_id),

// Jumps and branches
.branch_decision_i(branch_decision),
Expand All @@ -506,8 +499,6 @@ module cve2_core import cve2_pkg::*; #(
.instr_req_o (instr_req_int),
.pc_set_o (pc_set),
.pc_mux_o (pc_mux_id),
.nt_branch_mispredict_o(nt_branch_mispredict),
.nt_branch_addr_o (nt_branch_addr),
.exc_pc_mux_o (exc_pc_mux_id),
.exc_cause_o (exc_cause),
.icache_inval_o (icache_inval),
Expand Down
11 changes: 0 additions & 11 deletions rtl/cve2_id_stage.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,6 @@ module cve2_id_stage #(
input logic [31:0] instr_rdata_alu_i, // from IF-ID pipeline registers
input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers
input logic instr_is_compressed_i,
input logic instr_bp_taken_i,
output logic instr_req_o,
output logic instr_first_cycle_id_o,
output logic instr_valid_clear_o, // kill instr in IF-ID reg
Expand All @@ -49,8 +48,6 @@ module cve2_id_stage #(
// IF and ID stage signals
output logic pc_set_o,
output cve2_pkg::pc_sel_e pc_mux_o,
output logic nt_branch_mispredict_o,
output logic [31:0] nt_branch_addr_o,
output cve2_pkg::exc_pc_sel_e exc_pc_mux_o,
output cve2_pkg::exc_cause_e exc_cause_o,

Expand Down Expand Up @@ -496,7 +493,6 @@ module cve2_id_stage #(
.instr_i (instr_rdata_i),
.instr_compressed_i (instr_rdata_c_i),
.instr_is_compressed_i (instr_is_compressed_i),
.instr_bp_taken_i (instr_bp_taken_i),
.instr_fetch_err_i (instr_fetch_err_i),
.instr_fetch_err_plus2_i(instr_fetch_err_plus2_i),
.pc_id_i (pc_id_i),
Expand All @@ -510,7 +506,6 @@ module cve2_id_stage #(
.instr_req_o (instr_req_o),
.pc_set_o (pc_set_o),
.pc_mux_o (pc_mux_o),
.nt_branch_mispredict_o(nt_branch_mispredict_o),
.exc_pc_mux_o (exc_pc_mux_o),
.exc_cause_o (exc_cause_o),

Expand Down Expand Up @@ -664,12 +659,6 @@ module cve2_id_stage #(

end

// Holding branch_set/jump_set high for more than one cycle should not cause a functional issue.
// However it could generate needless prefetch buffer flushes and instruction fetches. The ID/EX
// designs ensures that this never happens for non-predicted branches.
`ASSERT(NeverDoubleBranch, branch_set & ~instr_bp_taken_i |=> ~branch_set)
`ASSERT(NeverDoubleJump, jump_set & ~instr_bp_taken_i |=> ~jump_set)

///////////////
// ID-EX FSM //
///////////////
Expand Down
63 changes: 13 additions & 50 deletions rtl/cve2_if_stage.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,8 +64,6 @@ module cve2_if_stage import cve2_pkg::*; #(
// instr_is_compressed_id_o = 1'b1
output logic instr_is_compressed_id_o, // compressed decoder thinks this
// is a compressed instr
output logic instr_bp_taken_o, // instruction was predicted to be
// a taken branch
output logic instr_fetch_err_o, // bus error on fetch
output logic instr_fetch_err_plus2_o, // bus error misaligned
output logic illegal_c_insn_id_o, // compressed decoder thinks this
Expand All @@ -80,9 +78,6 @@ module cve2_if_stage import cve2_pkg::*; #(
input logic instr_valid_clear_i, // clear instr valid bit in IF-ID
input logic pc_set_i, // set the PC to a new value
input pc_sel_e pc_mux_i, // selector for PC multiplexer
input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was
// mispredicted (predicted taken)
input logic [31:0] nt_branch_addr_i, // Not-taken branch address in ID/EX
input exc_pc_sel_e exc_pc_mux_i, // selects ISR address
input exc_cause_e exc_cause, // selects ISR address for
// vectorized interrupt lines
Expand Down Expand Up @@ -133,10 +128,7 @@ module cve2_if_stage import cve2_pkg::*; #(
logic illegal_c_insn;
logic instr_is_compressed;

logic if_instr_valid;
logic [31:0] if_instr_rdata;
logic [31:0] if_instr_addr;
logic if_instr_bus_err;
logic if_instr_pmp_err;
logic if_instr_err;
logic if_instr_err_plus2;
Expand All @@ -155,9 +147,6 @@ module cve2_if_stage import cve2_pkg::*; #(
logic illegal_c_instr_out;
logic instr_err_out;

logic predict_branch_taken;
logic [31:0] predict_branch_pc;

cve2_pkg::pc_sel_e pc_mux_internal;

logic [7:0] unused_boot_addr;
Expand Down Expand Up @@ -214,8 +203,6 @@ module cve2_if_stage import cve2_pkg::*; #(
.req_i ( req_i ),

.branch_i ( branch_req ),
.branch_mispredict_i ( nt_branch_mispredict_i ),
.mispredict_addr_i ( nt_branch_addr_i ),
.addr_i ( {fetch_addr_n[31:1], 1'b0} ),

.ready_i ( fetch_ready ),
Expand Down Expand Up @@ -260,11 +247,9 @@ module cve2_if_stage import cve2_pkg::*; #(
.req_i ( req_i ),

.branch_i ( branch_req ),
.branch_mispredict_i ( nt_branch_mispredict_i ),
.mispredict_addr_i ( nt_branch_addr_i ),
.addr_i ( {fetch_addr_n[31:1], 1'b0} ),

.ready_i ( fetch_ready ),
.ready_i ( id_in_ready_i ),
.valid_o ( fetch_valid ),
.rdata_o ( fetch_rdata ),
.addr_o ( fetch_addr ),
Expand Down Expand Up @@ -318,22 +303,22 @@ module cve2_if_stage import cve2_pkg::*; #(

assign unused_fetch_addr_n0 = fetch_addr_n[0];

assign branch_req = pc_set_i | predict_branch_taken;
assign branch_req = pc_set_i;

assign pc_if_o = if_instr_addr;
assign pc_if_o = fetch_addr;
assign if_busy_o = prefetch_busy;

// PMP errors
// An error can come from the instruction address, or the next instruction address for unaligned,
// uncompressed instructions.
assign if_instr_pmp_err = pmp_err_if_i |
(if_instr_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i);
(fetch_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i);

// Combine bus errors and pmp errors
assign if_instr_err = if_instr_bus_err | if_instr_pmp_err;
assign if_instr_err = fetch_err | if_instr_pmp_err;

// Capture the second half of the address for errors on the second part of an instruction
assign if_instr_err_plus2 = ((if_instr_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i) |
assign if_instr_err_plus2 = ((fetch_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i) |
fetch_err_plus2) & ~pmp_err_if_i;

// compressed instruction decoding, or more precisely compressed instruction
Expand All @@ -345,7 +330,7 @@ module cve2_if_stage import cve2_pkg::*; #(
.clk_i (clk_i),
.rst_ni (rst_ni),
.valid_i (fetch_valid & ~fetch_err),
.instr_i (if_instr_rdata),
.instr_i (fetch_rdata),
.instr_o (instr_decompressed),
.is_compressed_o(instr_is_compressed),
.illegal_instr_o(illegal_c_insn)
Expand Down Expand Up @@ -414,9 +399,9 @@ module cve2_if_stage import cve2_pkg::*; #(
// The ID stage becomes valid as soon as any instruction is registered in the ID stage flops.
// Note that the current instruction is squashed by the incoming pc_set_i signal.
// Valid is held until it is explicitly cleared (due to an instruction completing or an exception)
assign instr_valid_id_d = (if_instr_valid & id_in_ready_i & ~pc_set_i) |
assign instr_valid_id_d = (fetch_valid & id_in_ready_i & ~pc_set_i) |
(instr_valid_id_q & ~instr_valid_clear_i);
assign instr_new_id_d = if_instr_valid & id_in_ready_i;
assign instr_new_id_d = fetch_valid & id_in_ready_i;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
Expand Down Expand Up @@ -452,7 +437,7 @@ module cve2_if_stage import cve2_pkg::*; #(
instr_rdata_alu_id_o <= instr_out;
instr_fetch_err_o <= instr_err_out;
instr_fetch_err_plus2_o <= if_instr_err_plus2;
instr_rdata_c_id_o <= if_instr_rdata[15:0];
instr_rdata_c_id_o <= fetch_rdata[15:0];
instr_is_compressed_id_o <= instr_is_compressed_out;
illegal_c_insn_id_o <= illegal_c_instr_out;
pc_id_o <= pc_if_o;
Expand All @@ -461,12 +446,12 @@ module cve2_if_stage import cve2_pkg::*; #(
end else begin : g_instr_rdata_nr
always_ff @(posedge clk_i) begin
if (if_id_pipe_reg_we) begin
instr_rdata_id_o <= instr_out;
instr_rdata_id_o <= instr_decompressed;
// To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
instr_rdata_alu_id_o <= instr_out;
instr_rdata_alu_id_o <= instr_decompressed;
instr_fetch_err_o <= instr_err_out;
instr_fetch_err_plus2_o <= if_instr_err_plus2;
instr_rdata_c_id_o <= if_instr_rdata[15:0];
instr_rdata_c_id_o <= fetch_rdata[15:0];
instr_is_compressed_id_o <= instr_is_compressed_out;
illegal_c_insn_id_o <= illegal_c_instr_out;
pc_id_o <= pc_if_o;
Expand Down Expand Up @@ -508,35 +493,13 @@ module cve2_if_stage import cve2_pkg::*; #(
assign pc_mismatch_alert_o = 1'b0;
end

begin : g_no_branch_predictor
assign instr_bp_taken_o = 1'b0;
assign predict_branch_taken = 1'b0;
assign predict_branch_pc = 32'b0;

assign if_instr_valid = fetch_valid;
assign if_instr_rdata = fetch_rdata;
assign if_instr_addr = fetch_addr;
assign if_instr_bus_err = fetch_err;
assign fetch_ready = id_in_ready_i & ~stall_dummy_instr;
end

////////////////
// Assertions //
////////////////

// Selectors must be known/valid.
`ASSERT_KNOWN(IbexExcPcMuxKnown, exc_pc_mux_i)

begin : g_no_branch_predictor_asserts
`ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside {
PC_BOOT,
PC_JUMP,
PC_EXC,
PC_ERET,
PC_DRET},
pc_set_i)
end

// Boot address must be aligned to 256 bytes.
`ASSERT(IbexBootAddrUnaligned, boot_addr_i[7:0] == 8'h00)

Expand Down
Loading

0 comments on commit edf92ee

Please sign in to comment.