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sharedRuntime_x86_64.cpp
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sharedRuntime_x86_64.cpp
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/*
* Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#ifndef _WINDOWS
#include "alloca.h"
#endif
#include "asm/macroAssembler.hpp"
#include "asm/macroAssembler.inline.hpp"
#include "classfile/symbolTable.hpp"
#include "code/compiledIC.hpp"
#include "code/debugInfoRec.hpp"
#include "code/nativeInst.hpp"
#include "code/vtableStubs.hpp"
#include "compiler/oopMap.hpp"
#include "gc/shared/collectedHeap.hpp"
#include "gc/shared/gcLocker.hpp"
#include "gc/shared/barrierSet.hpp"
#include "gc/shared/barrierSetAssembler.hpp"
#include "interpreter/interpreter.hpp"
#include "logging/log.hpp"
#include "memory/resourceArea.hpp"
#include "memory/universe.hpp"
#include "oops/klass.inline.hpp"
#include "oops/method.inline.hpp"
#include "prims/methodHandles.hpp"
#include "runtime/continuation.hpp"
#include "runtime/continuationEntry.inline.hpp"
#include "runtime/globals.hpp"
#include "runtime/jniHandles.hpp"
#include "runtime/safepointMechanism.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/signature.hpp"
#include "runtime/stubRoutines.hpp"
#include "runtime/timerTrace.hpp"
#include "runtime/vframeArray.hpp"
#include "runtime/vm_version.hpp"
#include "utilities/align.hpp"
#include "utilities/checkedCast.hpp"
#include "utilities/formatBuffer.hpp"
#include "vmreg_x86.inline.hpp"
#ifdef COMPILER1
#include "c1/c1_Runtime1.hpp"
#endif
#ifdef COMPILER2
#include "opto/runtime.hpp"
#endif
#if INCLUDE_JVMCI
#include "jvmci/jvmciJavaClasses.hpp"
#endif
#define __ masm->
#ifdef PRODUCT
#define BLOCK_COMMENT(str) /* nothing */
#else
#define BLOCK_COMMENT(str) __ block_comment(str)
#endif // PRODUCT
const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
class RegisterSaver {
// Capture info about frame layout. Layout offsets are in jint
// units because compiler frame slots are jints.
#define XSAVE_AREA_BEGIN 160
#define XSAVE_AREA_YMM_BEGIN 576
#define XSAVE_AREA_EGPRS 960
#define XSAVE_AREA_OPMASK_BEGIN 1088
#define XSAVE_AREA_ZMM_BEGIN 1152
#define XSAVE_AREA_UPPERBANK 1664
#define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
#define DEF_YMM_OFFS(regnum) ymm ## regnum ## _off = ymm_off + (regnum)*16/BytesPerInt, ymm ## regnum ## H_off
#define DEF_ZMM_OFFS(regnum) zmm ## regnum ## _off = zmm_off + (regnum)*32/BytesPerInt, zmm ## regnum ## H_off
#define DEF_OPMASK_OFFS(regnum) opmask ## regnum ## _off = opmask_off + (regnum)*8/BytesPerInt, opmask ## regnum ## H_off
#define DEF_ZMM_UPPER_OFFS(regnum) zmm ## regnum ## _off = zmm_upper_off + (regnum-16)*64/BytesPerInt, zmm ## regnum ## H_off
enum layout {
fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
xmm_off = fpu_state_off + XSAVE_AREA_BEGIN/BytesPerInt, // offset in fxsave save area
DEF_XMM_OFFS(0),
DEF_XMM_OFFS(1),
// 2..15 are implied in range usage
ymm_off = xmm_off + (XSAVE_AREA_YMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt,
DEF_YMM_OFFS(0),
DEF_YMM_OFFS(1),
// 2..15 are implied in range usage
r31_off = xmm_off + (XSAVE_AREA_EGPRS - XSAVE_AREA_BEGIN)/BytesPerInt,
r31H_off,
r30_off, r30H_off,
r29_off, r29H_off,
r28_off, r28H_off,
r27_off, r27H_off,
r26_off, r26H_off,
r25_off, r25H_off,
r24_off, r24H_off,
r23_off, r23H_off,
r22_off, r22H_off,
r21_off, r21H_off,
r20_off, r20H_off,
r19_off, r19H_off,
r18_off, r18H_off,
r17_off, r17H_off,
r16_off, r16H_off,
opmask_off = xmm_off + (XSAVE_AREA_OPMASK_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt,
DEF_OPMASK_OFFS(0),
DEF_OPMASK_OFFS(1),
// 2..7 are implied in range usage
zmm_off = xmm_off + (XSAVE_AREA_ZMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt,
DEF_ZMM_OFFS(0),
DEF_ZMM_OFFS(1),
zmm_upper_off = xmm_off + (XSAVE_AREA_UPPERBANK - XSAVE_AREA_BEGIN)/BytesPerInt,
DEF_ZMM_UPPER_OFFS(16),
DEF_ZMM_UPPER_OFFS(17),
// 18..31 are implied in range usage
fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
fpu_stateH_end,
r15_off, r15H_off,
r14_off, r14H_off,
r13_off, r13H_off,
r12_off, r12H_off,
r11_off, r11H_off,
r10_off, r10H_off,
r9_off, r9H_off,
r8_off, r8H_off,
rdi_off, rdiH_off,
rsi_off, rsiH_off,
ignore_off, ignoreH_off, // extra copy of rbp
rsp_off, rspH_off,
rbx_off, rbxH_off,
rdx_off, rdxH_off,
rcx_off, rcxH_off,
rax_off, raxH_off,
// 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
align_off, alignH_off,
flags_off, flagsH_off,
// The frame sender code expects that rbp will be in the "natural" place and
// will override any oopMap setting for it. We must therefore force the layout
// so that it agrees with the frame sender code.
rbp_off, rbpH_off, // copy of rbp we will restore
return_off, returnH_off, // slot for return address
reg_save_size // size in compiler stack slots
};
public:
static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_wide_vectors);
static void restore_live_registers(MacroAssembler* masm, bool restore_wide_vectors = false);
// Offsets into the register save area
// Used by deoptimization when it is managing result register
// values on its own
static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
// During deoptimization only the result registers need to be restored,
// all the other values have already been extracted.
static void restore_result_registers(MacroAssembler* masm);
};
OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_wide_vectors) {
int off = 0;
int num_xmm_regs = XMMRegister::available_xmm_registers();
#if COMPILER2_OR_JVMCI
if (save_wide_vectors && UseAVX == 0) {
save_wide_vectors = false; // vectors larger than 16 byte long are supported only with AVX
}
assert(!save_wide_vectors || MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported");
#else
save_wide_vectors = false; // vectors are generated only by C2 and JVMCI
#endif
// Always make the frame size 16-byte aligned, both vector and non vector stacks are always allocated
int frame_size_in_bytes = align_up(reg_save_size*BytesPerInt, num_xmm_regs);
// OopMap frame size is in compiler stack slots (jint's) not bytes or words
int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
// CodeBlob frame size is in words.
int frame_size_in_words = frame_size_in_bytes / wordSize;
*total_frame_words = frame_size_in_words;
// Save registers, fpu state, and flags.
// We assume caller has already pushed the return address onto the
// stack, so rsp is 8-byte aligned here.
// We push rpb twice in this sequence because we want the real rbp
// to be under the return like a normal enter.
__ enter(); // rsp becomes 16-byte aligned here
__ pushf();
// Make sure rsp stays 16-byte aligned
__ subq(rsp, 8);
// Push CPU state in multiple of 16 bytes
__ save_legacy_gprs();
__ push_FPU_state();
// push cpu state handles this on EVEX enabled targets
if (save_wide_vectors) {
// Save upper half of YMM registers(0..15)
int base_addr = XSAVE_AREA_YMM_BEGIN;
for (int n = 0; n < 16; n++) {
__ vextractf128_high(Address(rsp, base_addr+n*16), as_XMMRegister(n));
}
if (VM_Version::supports_evex()) {
// Save upper half of ZMM registers(0..15)
base_addr = XSAVE_AREA_ZMM_BEGIN;
for (int n = 0; n < 16; n++) {
__ vextractf64x4_high(Address(rsp, base_addr+n*32), as_XMMRegister(n));
}
// Save full ZMM registers(16..num_xmm_regs)
base_addr = XSAVE_AREA_UPPERBANK;
off = 0;
int vector_len = Assembler::AVX_512bit;
for (int n = 16; n < num_xmm_regs; n++) {
__ evmovdqul(Address(rsp, base_addr+(off++*64)), as_XMMRegister(n), vector_len);
}
#if COMPILER2_OR_JVMCI
base_addr = XSAVE_AREA_OPMASK_BEGIN;
off = 0;
for(int n = 0; n < KRegister::number_of_registers; n++) {
__ kmov(Address(rsp, base_addr+(off++*8)), as_KRegister(n));
}
#endif
}
} else {
if (VM_Version::supports_evex()) {
// Save upper bank of XMM registers(16..31) for scalar or 16-byte vector usage
int base_addr = XSAVE_AREA_UPPERBANK;
off = 0;
int vector_len = VM_Version::supports_avx512vl() ? Assembler::AVX_128bit : Assembler::AVX_512bit;
for (int n = 16; n < num_xmm_regs; n++) {
__ evmovdqul(Address(rsp, base_addr+(off++*64)), as_XMMRegister(n), vector_len);
}
#if COMPILER2_OR_JVMCI
base_addr = XSAVE_AREA_OPMASK_BEGIN;
off = 0;
for(int n = 0; n < KRegister::number_of_registers; n++) {
__ kmov(Address(rsp, base_addr+(off++*8)), as_KRegister(n));
}
#endif
}
}
#if COMPILER2_OR_JVMCI
if (UseAPX) {
int base_addr = XSAVE_AREA_EGPRS;
off = 0;
for(int n = 16; n < Register::number_of_registers; n++) {
__ movq(Address(rsp, base_addr+(off++*8)), as_Register(n));
}
}
#endif
__ vzeroupper();
if (frame::arg_reg_save_area_bytes != 0) {
// Allocate argument register save area
__ subptr(rsp, frame::arg_reg_save_area_bytes);
}
// Set an oopmap for the call site. This oopmap will map all
// oop-registers and debug-info registers as callee-saved. This
// will allow deoptimization at this safepoint to find all possible
// debug-info recordings, as well as let GC find all oops.
OopMapSet *oop_maps = new OopMapSet();
OopMap* map = new OopMap(frame_size_in_slots, 0);
#define STACK_OFFSET(x) VMRegImpl::stack2reg((x))
map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg());
map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg());
map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg());
map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg());
// rbp location is known implicitly by the frame sender code, needs no oopmap
// and the location where rbp was saved by is ignored
map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg());
map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg());
if (UseAPX) {
map->set_callee_saved(STACK_OFFSET( r16_off ), r16->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r17_off ), r17->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r18_off ), r18->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r19_off ), r19->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r20_off ), r20->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r21_off ), r21->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r22_off ), r22->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r23_off ), r23->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r24_off ), r24->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r25_off ), r25->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r26_off ), r26->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r27_off ), r27->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r28_off ), r28->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r29_off ), r29->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r30_off ), r30->as_VMReg());
map->set_callee_saved(STACK_OFFSET( r31_off ), r31->as_VMReg());
}
// For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15,
// on EVEX enabled targets, we get it included in the xsave area
off = xmm0_off;
int delta = xmm1_off - off;
for (int n = 0; n < 16; n++) {
XMMRegister xmm_name = as_XMMRegister(n);
map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg());
off += delta;
}
if (UseAVX > 2) {
// Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets
off = zmm16_off;
delta = zmm17_off - off;
for (int n = 16; n < num_xmm_regs; n++) {
XMMRegister zmm_name = as_XMMRegister(n);
map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg());
off += delta;
}
}
#if COMPILER2_OR_JVMCI
if (save_wide_vectors) {
// Save upper half of YMM registers(0..15)
off = ymm0_off;
delta = ymm1_off - ymm0_off;
for (int n = 0; n < 16; n++) {
XMMRegister ymm_name = as_XMMRegister(n);
map->set_callee_saved(STACK_OFFSET(off), ymm_name->as_VMReg()->next(4));
off += delta;
}
if (VM_Version::supports_evex()) {
// Save upper half of ZMM registers(0..15)
off = zmm0_off;
delta = zmm1_off - zmm0_off;
for (int n = 0; n < 16; n++) {
XMMRegister zmm_name = as_XMMRegister(n);
map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg()->next(8));
off += delta;
}
}
}
#endif // COMPILER2_OR_JVMCI
// %%% These should all be a waste but we'll keep things as they were for now
if (true) {
map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next());
// rbp location is known implicitly by the frame sender code, needs no oopmap
map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next());
if (UseAPX) {
map->set_callee_saved(STACK_OFFSET( r16H_off ), r16->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r17H_off ), r17->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r18H_off ), r18->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r19H_off ), r19->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r20H_off ), r20->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r21H_off ), r21->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r22H_off ), r22->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r23H_off ), r23->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r24H_off ), r24->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r25H_off ), r25->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r26H_off ), r26->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r27H_off ), r27->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r28H_off ), r28->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r29H_off ), r29->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r30H_off ), r30->as_VMReg()->next());
map->set_callee_saved(STACK_OFFSET( r31H_off ), r31->as_VMReg()->next());
}
// For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15,
// on EVEX enabled targets, we get it included in the xsave area
off = xmm0H_off;
delta = xmm1H_off - off;
for (int n = 0; n < 16; n++) {
XMMRegister xmm_name = as_XMMRegister(n);
map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg()->next());
off += delta;
}
if (UseAVX > 2) {
// Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets
off = zmm16H_off;
delta = zmm17H_off - off;
for (int n = 16; n < num_xmm_regs; n++) {
XMMRegister zmm_name = as_XMMRegister(n);
map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg()->next());
off += delta;
}
}
}
return map;
}
void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_wide_vectors) {
int num_xmm_regs = XMMRegister::available_xmm_registers();
if (frame::arg_reg_save_area_bytes != 0) {
// Pop arg register save area
__ addptr(rsp, frame::arg_reg_save_area_bytes);
}
#if COMPILER2_OR_JVMCI
if (restore_wide_vectors) {
assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX");
assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported");
}
#else
assert(!restore_wide_vectors, "vectors are generated only by C2");
#endif
__ vzeroupper();
// On EVEX enabled targets everything is handled in pop fpu state
if (restore_wide_vectors) {
// Restore upper half of YMM registers (0..15)
int base_addr = XSAVE_AREA_YMM_BEGIN;
for (int n = 0; n < 16; n++) {
__ vinsertf128_high(as_XMMRegister(n), Address(rsp, base_addr+n*16));
}
if (VM_Version::supports_evex()) {
// Restore upper half of ZMM registers (0..15)
base_addr = XSAVE_AREA_ZMM_BEGIN;
for (int n = 0; n < 16; n++) {
__ vinsertf64x4_high(as_XMMRegister(n), Address(rsp, base_addr+n*32));
}
// Restore full ZMM registers(16..num_xmm_regs)
base_addr = XSAVE_AREA_UPPERBANK;
int vector_len = Assembler::AVX_512bit;
int off = 0;
for (int n = 16; n < num_xmm_regs; n++) {
__ evmovdqul(as_XMMRegister(n), Address(rsp, base_addr+(off++*64)), vector_len);
}
#if COMPILER2_OR_JVMCI
base_addr = XSAVE_AREA_OPMASK_BEGIN;
off = 0;
for (int n = 0; n < KRegister::number_of_registers; n++) {
__ kmov(as_KRegister(n), Address(rsp, base_addr+(off++*8)));
}
#endif
}
} else {
if (VM_Version::supports_evex()) {
// Restore upper bank of XMM registers(16..31) for scalar or 16-byte vector usage
int base_addr = XSAVE_AREA_UPPERBANK;
int off = 0;
int vector_len = VM_Version::supports_avx512vl() ? Assembler::AVX_128bit : Assembler::AVX_512bit;
for (int n = 16; n < num_xmm_regs; n++) {
__ evmovdqul(as_XMMRegister(n), Address(rsp, base_addr+(off++*64)), vector_len);
}
#if COMPILER2_OR_JVMCI
base_addr = XSAVE_AREA_OPMASK_BEGIN;
off = 0;
for (int n = 0; n < KRegister::number_of_registers; n++) {
__ kmov(as_KRegister(n), Address(rsp, base_addr+(off++*8)));
}
#endif
}
}
#if COMPILER2_OR_JVMCI
if (UseAPX) {
int base_addr = XSAVE_AREA_EGPRS;
int off = 0;
for (int n = 16; n < Register::number_of_registers; n++) {
__ movq(as_Register(n), Address(rsp, base_addr+(off++*8)));
}
}
#endif
// Recover CPU state
__ pop_FPU_state();
__ restore_legacy_gprs();
__ addq(rsp, 8);
__ popf();
// Get the rbp described implicitly by the calling convention (no oopMap)
__ pop(rbp);
}
void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
// Just restore result register. Only used by deoptimization. By
// now any callee save register that needs to be restored to a c2
// caller of the deoptee has been extracted into the vframeArray
// and will be stuffed into the c2i adapter we create for later
// restoration so only result registers need to be restored here.
// Restore fp result register
__ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
// Restore integer result register
__ movptr(rax, Address(rsp, rax_offset_in_bytes()));
__ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
// Pop all of the register save are off the stack except the return address
__ addptr(rsp, return_offset_in_bytes());
}
// Is vector's size (in bytes) bigger than a size saved by default?
// 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions.
bool SharedRuntime::is_wide_vector(int size) {
return size > 16;
}
// ---------------------------------------------------------------------------
// Read the array of BasicTypes from a signature, and compute where the
// arguments should go. Values in the VMRegPair regs array refer to 4-byte
// quantities. Values less than VMRegImpl::stack0 are registers, those above
// refer to 4-byte stack slots. All stack slots are based off of the stack pointer
// as framesizes are fixed.
// VMRegImpl::stack0 refers to the first slot 0(sp).
// and VMRegImpl::stack0+1 refers to the memory word 4-byes higher.
// Register up to Register::number_of_registers are the 64-bit
// integer registers.
// Note: the INPUTS in sig_bt are in units of Java argument words, which are
// either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
// units regardless of build. Of course for i486 there is no 64 bit build
// The Java calling convention is a "shifted" version of the C ABI.
// By skipping the first C ABI register we can call non-static jni methods
// with small numbers of arguments without having to shuffle the arguments
// at all. Since we control the java ABI we ought to at least get some
// advantage out of it.
int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
int total_args_passed) {
// Create the mapping between argument positions and
// registers.
static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
};
static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
j_farg0, j_farg1, j_farg2, j_farg3,
j_farg4, j_farg5, j_farg6, j_farg7
};
uint int_args = 0;
uint fp_args = 0;
uint stk_args = 0;
for (int i = 0; i < total_args_passed; i++) {
switch (sig_bt[i]) {
case T_BOOLEAN:
case T_CHAR:
case T_BYTE:
case T_SHORT:
case T_INT:
if (int_args < Argument::n_int_register_parameters_j) {
regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
} else {
stk_args = align_up(stk_args, 2);
regs[i].set1(VMRegImpl::stack2reg(stk_args));
stk_args += 1;
}
break;
case T_VOID:
// halves of T_LONG or T_DOUBLE
assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
regs[i].set_bad();
break;
case T_LONG:
assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
// fall through
case T_OBJECT:
case T_ARRAY:
case T_ADDRESS:
if (int_args < Argument::n_int_register_parameters_j) {
regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
} else {
stk_args = align_up(stk_args, 2);
regs[i].set2(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
}
break;
case T_FLOAT:
if (fp_args < Argument::n_float_register_parameters_j) {
regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
} else {
stk_args = align_up(stk_args, 2);
regs[i].set1(VMRegImpl::stack2reg(stk_args));
stk_args += 1;
}
break;
case T_DOUBLE:
assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
if (fp_args < Argument::n_float_register_parameters_j) {
regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
} else {
stk_args = align_up(stk_args, 2);
regs[i].set2(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
}
break;
default:
ShouldNotReachHere();
break;
}
}
return stk_args;
}
// Same as java_calling_convention() but for multiple return
// values. There's no way to store them on the stack so if we don't
// have enough registers, multiple values can't be returned.
const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j+1;
const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
int SharedRuntime::java_return_convention(const BasicType *sig_bt,
VMRegPair *regs,
int total_args_passed) {
// Create the mapping between argument positions and
// registers.
static const Register INT_ArgReg[java_return_convention_max_int] = {
rax, j_rarg5, j_rarg4, j_rarg3, j_rarg2, j_rarg1, j_rarg0
};
static const XMMRegister FP_ArgReg[java_return_convention_max_float] = {
j_farg0, j_farg1, j_farg2, j_farg3,
j_farg4, j_farg5, j_farg6, j_farg7
};
uint int_args = 0;
uint fp_args = 0;
for (int i = 0; i < total_args_passed; i++) {
switch (sig_bt[i]) {
case T_BOOLEAN:
case T_CHAR:
case T_BYTE:
case T_SHORT:
case T_INT:
if (int_args < Argument::n_int_register_parameters_j+1) {
regs[i].set1(INT_ArgReg[int_args]->as_VMReg());
int_args++;
} else {
return -1;
}
break;
case T_VOID:
// halves of T_LONG or T_DOUBLE
assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
regs[i].set_bad();
break;
case T_LONG:
assert(sig_bt[i + 1] == T_VOID, "expecting half");
// fall through
case T_OBJECT:
case T_ARRAY:
case T_ADDRESS:
case T_METADATA:
if (int_args < Argument::n_int_register_parameters_j+1) {
regs[i].set2(INT_ArgReg[int_args]->as_VMReg());
int_args++;
} else {
return -1;
}
break;
case T_FLOAT:
if (fp_args < Argument::n_float_register_parameters_j) {
regs[i].set1(FP_ArgReg[fp_args]->as_VMReg());
fp_args++;
} else {
return -1;
}
break;
case T_DOUBLE:
assert(sig_bt[i + 1] == T_VOID, "expecting half");
if (fp_args < Argument::n_float_register_parameters_j) {
regs[i].set2(FP_ArgReg[fp_args]->as_VMReg());
fp_args++;
} else {
return -1;
}
break;
default:
ShouldNotReachHere();
break;
}
}
return int_args + fp_args;
}
// Patch the callers callsite with entry to compiled code if it exists.
static void patch_callers_callsite(MacroAssembler *masm) {
Label L;
__ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
__ jcc(Assembler::equal, L);
// Save the current stack pointer
__ mov(r13, rsp);
// Schedule the branch target address early.
// Call into the VM to patch the caller, then jump to compiled callee
// rax isn't live so capture return address while we easily can
__ movptr(rax, Address(rsp, 0));
// align stack so push_CPU_state doesn't fault
__ andptr(rsp, -(StackAlignmentInBytes));
__ push_CPU_state();
__ vzeroupper();
// VM needs caller's callsite
// VM needs target method
// This needs to be a long call since we will relocate this adapter to
// the codeBuffer and it may not reach
// Allocate argument register save area
if (frame::arg_reg_save_area_bytes != 0) {
__ subptr(rsp, frame::arg_reg_save_area_bytes);
}
__ mov(c_rarg0, rbx);
__ mov(c_rarg1, rax);
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
// De-allocate argument register save area
if (frame::arg_reg_save_area_bytes != 0) {
__ addptr(rsp, frame::arg_reg_save_area_bytes);
}
__ vzeroupper();
__ pop_CPU_state();
// restore sp
__ mov(rsp, r13);
__ bind(L);
}
// For each inline type argument, sig includes the list of fields of
// the inline type. This utility function computes the number of
// arguments for the call if inline types are passed by reference (the
// calling convention the interpreter expects).
static int compute_total_args_passed_int(const GrowableArray<SigEntry>* sig_extended) {
int total_args_passed = 0;
if (InlineTypePassFieldsAsArgs) {
for (int i = 0; i < sig_extended->length(); i++) {
BasicType bt = sig_extended->at(i)._bt;
if (bt == T_METADATA) {
// In sig_extended, an inline type argument starts with:
// T_METADATA, followed by the types of the fields of the
// inline type and T_VOID to mark the end of the value
// type. Inline types are flattened so, for instance, in the
// case of an inline type with an int field and an inline type
// field that itself has 2 fields, an int and a long:
// T_METADATA T_INT T_METADATA T_INT T_LONG T_VOID (second
// slot for the T_LONG) T_VOID (inner inline type) T_VOID
// (outer inline type)
total_args_passed++;
int vt = 1;
do {
i++;
BasicType bt = sig_extended->at(i)._bt;
BasicType prev_bt = sig_extended->at(i-1)._bt;
if (bt == T_METADATA) {
vt++;
} else if (bt == T_VOID &&
prev_bt != T_LONG &&
prev_bt != T_DOUBLE) {
vt--;
}
} while (vt != 0);
} else {
total_args_passed++;
}
}
} else {
total_args_passed = sig_extended->length();
}
return total_args_passed;
}
static void gen_c2i_adapter_helper(MacroAssembler* masm,
BasicType bt,
BasicType prev_bt,
size_t size_in_bytes,
const VMRegPair& reg_pair,
const Address& to,
int extraspace,
bool is_oop) {
if (bt == T_VOID) {
assert(prev_bt == T_LONG || prev_bt == T_DOUBLE, "missing half");
return;
}
// Say 4 args:
// i st_off
// 0 32 T_LONG
// 1 24 T_VOID
// 2 16 T_OBJECT
// 3 8 T_BOOL
// - 0 return address
//
// However to make thing extra confusing. Because we can fit a long/double in
// a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
// leaves one slot empty and only stores to a single slot. In this case the
// slot that is occupied is the T_VOID slot. See I said it was confusing.
bool wide = (size_in_bytes == wordSize);
VMReg r_1 = reg_pair.first();
VMReg r_2 = reg_pair.second();
assert(r_2->is_valid() == wide, "invalid size");
if (!r_1->is_valid()) {
assert(!r_2->is_valid(), "must be invalid");
return;
}
if (!r_1->is_XMMRegister()) {
Register val = rax;
if (r_1->is_stack()) {
int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
__ load_sized_value(val, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
} else {
val = r_1->as_Register();
}
assert_different_registers(to.base(), val, rscratch1);
if (is_oop) {
__ push(r13);
__ push(rbx);
__ store_heap_oop(to, val, rscratch1, r13, rbx, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
__ pop(rbx);
__ pop(r13);
} else {
__ store_sized_value(to, val, size_in_bytes);
}
} else {
if (wide) {
__ movdbl(to, r_1->as_XMMRegister());
} else {
__ movflt(to, r_1->as_XMMRegister());
}
}
}
static void gen_c2i_adapter(MacroAssembler *masm,
const GrowableArray<SigEntry>* sig_extended,
const VMRegPair *regs,
bool requires_clinit_barrier,
address& c2i_no_clinit_check_entry,
Label& skip_fixup,
address start,
OopMapSet* oop_maps,
int& frame_complete,
int& frame_size_in_words,
bool alloc_inline_receiver) {
if (requires_clinit_barrier && VM_Version::supports_fast_class_init_checks()) {
Label L_skip_barrier;
Register method = rbx;
{ // Bypass the barrier for non-static methods
Register flags = rscratch1;
__ movl(flags, Address(method, Method::access_flags_offset()));
__ testl(flags, JVM_ACC_STATIC);
__ jcc(Assembler::zero, L_skip_barrier); // non-static
}
Register klass = rscratch1;
__ load_method_holder(klass, method);
__ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
__ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
__ bind(L_skip_barrier);
c2i_no_clinit_check_entry = __ pc();
}
BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
bs->c2i_entry_barrier(masm);
// Before we get into the guts of the C2I adapter, see if we should be here
// at all. We've come from compiled code and are attempting to jump to the
// interpreter, which means the caller made a static call to get here
// (vcalls always get a compiled target if there is one). Check for a
// compiled target. If there is one, we need to patch the caller's call.
patch_callers_callsite(masm);
__ bind(skip_fixup);
if (InlineTypePassFieldsAsArgs) {
// Is there an inline type argument?
bool has_inline_argument = false;
for (int i = 0; i < sig_extended->length() && !has_inline_argument; i++) {
has_inline_argument = (sig_extended->at(i)._bt == T_METADATA);
}
if (has_inline_argument) {
// There is at least an inline type argument: we're coming from
// compiled code so we have no buffers to back the inline types.
// Allocate the buffers here with a runtime call.
OopMap* map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_vectors*/ false);
frame_complete = __ offset();
__ set_last_Java_frame(noreg, noreg, nullptr, rscratch1);
__ mov(c_rarg0, r15_thread);
__ mov(c_rarg1, rbx);
__ mov64(c_rarg2, (int64_t)alloc_inline_receiver);
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::allocate_inline_types)));
oop_maps->add_gc_map((int)(__ pc() - start), map);
__ reset_last_Java_frame(false);
RegisterSaver::restore_live_registers(masm);
Label no_exception;
__ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
__ jcc(Assembler::equal, no_exception);
__ movptr(Address(r15_thread, JavaThread::vm_result_offset()), NULL_WORD);
__ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
__ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
__ bind(no_exception);
// We get an array of objects from the runtime call
__ get_vm_result(rscratch2, r15_thread); // Use rscratch2 (r11) as temporary because rscratch1 (r10) is trashed by movptr()
__ get_vm_result_2(rbx, r15_thread); // TODO: required to keep the callee Method live?
}
}
// Since all args are passed on the stack, total_args_passed *
// Interpreter::stackElementSize is the space we need.
int total_args_passed = compute_total_args_passed_int(sig_extended);
assert(total_args_passed >= 0, "total_args_passed is %d", total_args_passed);
int extraspace = (total_args_passed * Interpreter::stackElementSize);
// stack is aligned, keep it that way
// This is not currently needed or enforced by the interpreter, but
// we might as well conform to the ABI.
extraspace = align_up(extraspace, 2*wordSize);
// set senderSP value
__ lea(r13, Address(rsp, wordSize));
#ifdef ASSERT
__ check_stack_alignment(r13, "sender stack not aligned");
#endif
if (extraspace > 0) {
// Pop the return address
__ pop(rax);
__ subptr(rsp, extraspace);
// Push the return address
__ push(rax);
// Account for the return address location since we store it first rather
// than hold it in a register across all the shuffling
extraspace += wordSize;
}
#ifdef ASSERT
__ check_stack_alignment(rsp, "callee stack not aligned", wordSize, rax);
#endif
// Now write the args into the outgoing interpreter space
// next_arg_comp is the next argument from the compiler point of
// view (inline type fields are passed in registers/on the stack). In
// sig_extended, an inline type argument starts with: T_METADATA,
// followed by the types of the fields of the inline type and T_VOID
// to mark the end of the inline type. ignored counts the number of
// T_METADATA/T_VOID. next_vt_arg is the next inline type argument:
// used to get the buffer for that argument from the pool of buffers
// we allocated above and want to pass to the
// interpreter. next_arg_int is the next argument from the
// interpreter point of view (inline types are passed by reference).