monitor: Dont require knowning PIPELINE in monitor

This makes configuring a new pipeline only require the CPU_OPTION parameter and not require extra `defines as well. I am using this in mor1kx-generic with or1k-tests to automatically test the cappuccino and espresso pipelines by just passing a command line switch to the test.
openrisc · Mar 6, 2019 · 16d2fa1 · 16d2fa1
1 parent aa4ea5a
commit 16d2fa1
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Showing 2 changed files with 57 additions and 5 deletions.
diff --git a/bench/verilog/mor1kx_monitor.v b/bench/verilog/mor1kx_monitor.v
@@ -25,15 +25,14 @@
 `ifndef CPU_WRAPPER
  `define CPU_WRAPPER `MOR1KX_INST.mor1kx_cpu
 `endif
-`define CPU_INST `CPU_WRAPPER.`MOR1KX_CPU_PIPELINE.mor1kx_cpu
 `define EXECUTE_STAGE_INSN `CPU_WRAPPER.monitor_execute_insn
 `define EXECUTE_STAGE_ADV `CPU_WRAPPER.monitor_execute_advance
 `define CPU_clk `CPU_WRAPPER.monitor_clk
 `define CPU_FLAG `CPU_WRAPPER.monitor_flag
 `define CPU_SR `CPU_WRAPPER.monitor_spr_sr
 `define EXECUTE_PC `CPU_WRAPPER.monitor_execute_pc
-`define GPR_GET(x) `CPU_INST.get_gpr(x)
-`define GPR_SET(x, y) `CPU_INST.set_gpr(x, y)
+`define GPR_GET(x) `CPU_WRAPPER.monitor.get_gpr(x)
+`define GPR_SET(x, y) `CPU_WRAPPER.monitor.set_gpr(x, y)
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_cpu.v b/rtl/verilog/mor1kx_cpu.v
@@ -198,6 +198,58 @@ module mor1kx_cpu
    wire [OPTION_OPERAND_WIDTH-1:0]   monitor_spr_esr/* verilator public */;
    wire 			     monitor_branch_mispredict/* verilator public */;
 
+	// synthesis translate_off
+`ifndef SYNTHESIS
+   /* Provide interface hooks for register functions. */
+   generate
+      if (OPTION_CPU=="CAPPUCCINO") begin : monitor
+
+`include "mor1kx_utils.vh"
+         localparam RF_ADDR_WIDTH = calc_rf_addr_width(OPTION_RF_ADDR_WIDTH,
+                                                       OPTION_RF_NUM_SHADOW_GPR);
+
+         function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
+            // verilator public
+            input [RF_ADDR_WIDTH-1:0] gpr_num;
+            get_gpr = cappuccino.mor1kx_cpu.get_gpr(gpr_num);
+         endfunction
+         task set_gpr;
+            // verilator public
+            input [RF_ADDR_WIDTH-1:0] gpr_num;
+            input [OPTION_OPERAND_WIDTH-1:0] gpr_value;
+            cappuccino.mor1kx_cpu.set_gpr(gpr_num, gpr_value);
+         endtask
+      end
+      if (OPTION_CPU=="ESPRESSO") begin : monitor
+         function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
+            // verilator public
+            input [15:0] gpr_num;
+            get_gpr = espresso.mor1kx_cpu.get_gpr(gpr_num);
+         endfunction
+         task set_gpr;
+            // verilator public
+            input [15:0] gpr_num;
+            input [OPTION_OPERAND_WIDTH-1:0] gpr_value;
+            espresso.mor1kx_cpu.set_gpr(gpr_num, gpr_value);
+         endtask
+      end
+      /* verilator lint_off WIDTH */
+      if (OPTION_CPU=="PRONTO_ESPRESSO") begin : monitor
+         function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
+            // verilator public
+            input [15:0] gpr_num;
+            get_gpr = prontoespresso.mor1kx_cpu.get_gpr(gpr_num);
+         endfunction
+         task set_gpr;
+            // verilator public
+            input [15:0] gpr_num;
+            input [OPTION_OPERAND_WIDTH-1:0] gpr_value;
+            prontoespresso.mor1kx_cpu.set_gpr(gpr_num, gpr_value);
+         endtask
+      end
+   endgenerate
+`endif
+	// synthesis translate_on
 
    generate
       /* verilator lint_off WIDTH */
@@ -331,7 +383,7 @@ module mor1kx_cpu
 	    .snoop_adr_i		(snoop_adr_i[31:0]),
 	    .snoop_en_i			(snoop_en_i));
 
-	 // synthesis translate_off
+	// synthesis translate_off
 `ifndef SYNTHESIS
 
 	 assign monitor_flag =  monitor_flag_set ? 1 :
@@ -358,8 +410,9 @@ module mor1kx_cpu
 
         assign monitor_execute_insn = monitor_execute_insn_reg;
 
+
 `endif
-	 // synthesis translate_on
+	// synthesis translate_on
 
 
       end // block: cappuccino