cappuccino/fetch: deassert ibus_req on rst

openrisc · May 9, 2014 · e0e2f05 · e0e2f05
1 parent aa77169
commit e0e2f05
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/rtl/verilog/mor1kx_fetch_cappuccino.v b/rtl/verilog/mor1kx_fetch_cappuccino.v
@@ -423,8 +423,10 @@ module mor1kx_fetch_cappuccino
 	  state <= IDLE;
       endcase // case (state)
 
-      if (rst)
-	state <= IDLE;
+      if (rst) begin
+	 ibus_req <= 0;
+	 state <= IDLE;
+      end
    end
 
    always @(posedge clk `OR_ASYNC_RST)