Generation of _soc_inthandlers.h for Zephyr #7849
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sunilkumardommati
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@sunilkumardommati you may want to ask on Zephyr project, but @andyross may be able to help you here too. |
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@andyross, could you please let us know your inputs on this issue? |
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@lgirdwood , we've got inputs in Zephyr devel forum that we need to run the xtensa_intgen.tmpl through the toolchain's preprocessor, and then use xtensa_intgen.py to process the output. |
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Hi,
We are working on porting Zephyr to our platform.
We are not sure on how to generate the _soc_inthandlers.h file which is placed at zephyr\soc\xtensa\soc_vendor\soc\include path.
I tried to generate using, zephyr\arch\xtensa\core\xtensa_intgen.py with our platform specific core-isa.h as input.
But its only producing the following code but not complete interrupt handlers.
`/*
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
static inline int _xtensa_handle_one_int0(unsigned int mask)
{
return 0;
}
`
please let me know if I’m missing anything here.
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