Enable/Disable all interrupts for aspirin for event handler

paparazzi · Apr 29, 2011 · 8e0aeb1 · 8e0aeb1
1 parent da6e1f4
commit 8e0aeb1
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Showing 2 changed files with 29 additions and 11 deletions.
diff --git a/sw/airborne/arch/stm32/subsystems/imu/imu_aspirin_arch.c b/sw/airborne/arch/stm32/subsystems/imu/imu_aspirin_arch.c
@@ -38,6 +38,15 @@ void imu_aspirin_arch_int_enable(void) {
   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
   NVIC_Init(&NVIC_InitStructure);
 
+  /* Enable DMA1 channel4 IRQ Channel ( SPI RX) */
+  NVIC_InitTypeDef NVIC_init_struct = {
+    .NVIC_IRQChannel = DMA1_Channel4_IRQn,
+    .NVIC_IRQChannelPreemptionPriority = 0,
+    .NVIC_IRQChannelSubPriority = 0,
+    .NVIC_IRQChannelCmd = ENABLE
+  };
+  NVIC_Init(&NVIC_init_struct);
+
 }
 
 void imu_aspirin_arch_int_disable(void) {
@@ -57,6 +66,15 @@ void imu_aspirin_arch_int_disable(void) {
   NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
   NVIC_Init(&NVIC_InitStructure);
 
+  /* Enable DMA1 channel4 IRQ Channel ( SPI RX) */
+  NVIC_InitTypeDef NVIC_init_struct = {
+    .NVIC_IRQChannel = DMA1_Channel4_IRQn,
+    .NVIC_IRQChannelPreemptionPriority = 0,
+    .NVIC_IRQChannelSubPriority = 0,
+    .NVIC_IRQChannelCmd = DISABLE
+  };
+  NVIC_Init(&NVIC_init_struct);
+
 }
 
 void imu_aspirin_arch_init(void) {
@@ -143,14 +161,6 @@ void imu_aspirin_arch_init(void) {
   SPI_InitStructure.SPI_CRCPolynomial = 7;
   SPI_Init(SPI2, &SPI_InitStructure);
 
-  /* Enable DMA1 channel4 IRQ Channel ( SPI RX) */
-  NVIC_InitTypeDef NVIC_init_struct = {
-    .NVIC_IRQChannel = DMA1_Channel4_IRQn,
-    .NVIC_IRQChannelPreemptionPriority = 0,
-    .NVIC_IRQChannelSubPriority = 0,
-    .NVIC_IRQChannelCmd = ENABLE
-  };
-  NVIC_Init(&NVIC_init_struct);
 
   /* Enable SPI_2 DMA clock ---------------------------------------------------*/
   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
@@ -268,6 +278,15 @@ void exti2_irq_handler(void) {
  */
 void dma1_c4_irq_handler(void) {
   Adxl345Unselect();
+  if (DMA_GetITStatus(DMA1_IT_TC4)) {
+		// clear int pending bit
+		DMA_ClearITPendingBit(DMA1_IT_GL4);
+
+    // mark as available
+    imu_aspirin.accel_available = TRUE;
+	}
+
+  // disable DMA Channel
   DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, DISABLE);
   /* Disable SPI_2 Rx and TX request */
   SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, DISABLE);
@@ -276,5 +295,4 @@ void dma1_c4_irq_handler(void) {
   DMA_Cmd(DMA1_Channel4, DISABLE);
   DMA_Cmd(DMA1_Channel5, DISABLE);
 
-  imu_aspirin.accel_available = TRUE;
 }
diff --git a/sw/airborne/subsystems/imu/imu_aspirin.h b/sw/airborne/subsystems/imu/imu_aspirin.h
@@ -127,14 +127,14 @@ static inline void imu_aspirin_event(void (* _gyro_handler)(void), void (* _acce
 {
   if (imu_aspirin.status == AspirinStatusUninit) return;
 
-  //imu_aspirin_arch_int_disable();
+  imu_aspirin_arch_int_disable();
   if (imu_aspirin.accel_available) {
     imu_aspirin.time_since_last_accel_reading = 0;
     imu_aspirin.accel_available = FALSE;
     accel_copy_spi();
     _accel_handler();
   }
-  //imu_aspirin_arch_int_enable();
+  imu_aspirin_arch_int_enable();
 
   // Reset everything if we've been waiting too long
   if (imu_aspirin.time_since_last_reading > ASPIRIN_GYRO_TIMEOUT) {