Design, simulation and implementation of a direct-mapped cache memory system in VHDL using Altera Quartus Prime and DE0_CV FPGA development kit, and compare it to a reference system without cache memory to verify the performance enhancement.
- Open Guidelines__P2_W17.pdf
- Review FinalProjectFico_docs/FinalProjectFico.mp4 and FinalProjectFico_docs/Project_Report.pdf
- Open SimpleCompArch.qar archive project, compile and simulate with ModelSim, set time simulation to 17 ns to see all resultant elements of matrix C.
- Project done in Quartus 16.1 and ModelSim 10.5b
- FinalProjectFico.mp4 uploaded to https://www.youtube.com/watch?v=Zvd96RGTEjk
Coursework project:
- University of New Brunswick, Universidad Mayor de San Andrés
- Module: ECE6733 - Computer Architecture Performance +
- Prof. Eduardo Castillo
Based on Simple Microprocessor Design (ESD Book Chapter 3),
originally created by Weijun Zhang, Copyright 2001, http://esd.cs.ucr.edu/labs/tutorial/