define mem ports domain from signal keyword, not from assign attribute

[github-4o]

from nyanMigen import nyanify


@nyanify(generics_file="config.json")
class ram:
    def elaborate(self, platform):
        wr_en = Signal()
        wr_addr = Signal(aw)
        wr_data = Signal(dw)
        rd_addr = Signal(aw)
        rd_data = Signal(dw)                                                                                                                     
        Memory(width = dw, depth = 2**aw, we = wr_en, wa = wr_addr, wd = sync.wr_data, ra = rd_addr, rd = rd_data)

->

from nyanMigen import nyanify


@nyanify(generics_file="config.json")
class ram:
    def elaborate(self, platform):
        wr_en = Signal()
        wr_addr = Signal(aw)
        wr_data = Signal(dw, domain = 'sync')
        rd_addr = Signal(aw)
        rd_data = Signal(dw)                                                                                                                     
        Memory(width = dw, depth = 2**aw, we = wr_en, wa = wr_addr, wd = wr_data, ra = rd_addr, rd = rd_data)