Pin does not exist #16
Comments
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I tried to reinstall litexcnc from sources : root@debian:/usr/src/python3.11# pip uninstall litexcnc As you see, litexcnc driver is not compiling on Debian Bookworm. |
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I compilled LiteX-CNC again, but without " git checkout 11-add-external-extensions-to-litexcnc". BTW. What Debian with what Linuxcnc is used for testing LiteX-CNC ? |
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I bet its preeempt: kernel-mode RTAI installation can not be used with Mesa Ethernet-interfaced cards. |
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I found. After changing "net blink siggen.0.clock => test_PWM_GPIO.gpio.j1:1.out" to "net blink siggen.0.clock => test_PWM_GPIO.gpio.00.out" (00 instead j1:1) example works and I got "blink" signal on expected pin. |
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Thanks for pointing this out. Here the documentation is lagging behind the development I'm afraid:
With above mentioned branch, one can build the firmware as follows: litexcnc build_firmware <config_file>.json --build -a In above command:
Also, the structure of the HAL file has changed a little as well, see example below: The connections is a comma-separated list with connections (yes, you can add multiple cards if you would like, just name both cards differently in that case). The format of a connection string is |
Used and compiled/install Litex-CNC with extensions. Now, when try litexcnc --build, I got : ValueError: Field |
Yesterday you wrote post #17 (comment) with json config example. Did you change the syntax of the configuration files? |
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@ Author I got it. { } There are two problems.
Could you write a short file with the new rules, but using all the modules. |
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Please fin below a working example of my lathe. {
"board_name": "EMCO5",
"board_type": "5A-75E v6.0",
"clock_frequency": 35000000,
"ethphy": {
"tx_delay": 0
},
"etherbone": {
"ip_address": "10.0.0.10",
"mac_address": "0x10e2d5000000"
},
"modules": [
{
"module_type": "gpio",
"instances": [
{"direction": "in", "pin":"j1:0", "name":"home-x"},
{"direction": "in", "pin":"j1:1", "name":"home-z"},
{"direction": "in", "pin":"j1:5", "name":"reset-feed-override"},
{"direction": "in", "pin":"j2:2", "name":"reset-rapid-override"},
{"direction": "in", "pin":"j2:6", "name":"reset-spindle-override"},
{"direction": "in", "pin":"j3:0", "name":"axis-x-selected"},
{"direction": "in", "pin":"j3:1", "name":"axis-z-selected"},
{"direction": "in", "pin":"j3:2"},
{"direction": "in", "pin":"j3:4"},
{"direction": "in", "pin":"j3:5"},
{"direction": "in", "pin":"j3:6"},
{"direction": "in", "pin":"j4:0", "name":"speed1-selected"},
{"direction": "in", "pin":"j4:1", "name":"speed2-selected"},
{"direction": "in", "pin":"j4:2", "name":"speed3-selected"},
{"direction": "in", "pin":"j4:4", "name":"start-button"},
{"direction": "in", "pin":"j4:5", "name":"feed-hold-button"},
{"direction": "in", "pin":"j4:6", "name":"stop-button"},
{"direction": "in", "pin":"j6:0"},
{"direction": "in", "pin":"j6:1"},
{"direction": "in", "pin":"j6:2"},
{"direction": "in", "pin":"j6:4", "name":"alarm-spindle"},
{"direction": "in", "pin":"j6:5", "name":"alarm-z"},
{"direction": "in", "pin":"j6:6", "name":"alarm-x"},
{"direction": "out", "pin":"j15:0", "name":"rapid-override-LED"},
{"direction": "out", "pin":"j15:1", "name":"feed-override-LED"},
{"direction": "out", "pin":"j15:2", "name":"spindle-override-LED"},
{"direction": "out", "pin":"j15:4"},
{"direction": "out", "pin":"j15:5"},
{"direction": "out", "pin":"j15:6"},
{"direction": "out", "pin":"j16:0", "name":"stop-LED"},
{"direction": "out", "pin":"j16:1", "name":"pause-LED"},
{"direction": "out", "pin":"j16:2", "name":"start-LED"},
{"direction": "out", "pin":"j16:4"}
]
}, {
"module_type": "encoder",
"instances": [
{"name":"rapid-override", "pin_A":"j1:4", "pin_B":"j1:2"},
{"name":"feed-override", "pin_A":"j1:6", "pin_B":"j2:1"},
{"name":"spindle-override", "pin_A":"j2:5", "pin_B":"j2:4"},
{"name":"mpg", "pin_A":"j8:0", "pin_B":"j8:1"},
{"name":"spindle", "pin_A":"j8:4", "pin_B":"j8:5", "pin_Z":"j8:6"}
]
}, {
"module_type": "stepgen",
"instances": [
{
"pins" : {
"stepgen_type": "step_dir_differential",
"step_pos_pin": "j9:6",
"step_neg_pin": "j9:5",
"dir_pos_pin": "j9:4",
"dir_neg_pin": "j9:2"
},
"soft_stop": true
}, {
"pins" : {
"stepgen_type": "step_dir_differential",
"step_pos_pin": "j9:1",
"step_neg_pin": "j9:0",
"dir_pos_pin": "j10:6",
"dir_neg_pin": "j10:5"
},
"soft_stop": true
}, {
"pins" : {
"stepgen_type": "step_dir_differential",
"step_pos_pin": "j10:4",
"step_neg_pin": "j10:2",
"dir_pos_pin": "j10:1",
"dir_neg_pin": "j10:0"
},
"soft_stop": true
}
]
}
]
}You cannot rename a pin of the stepgen, but you can rename the stepgen instance, i.e: {
...
"module_type": "stepgen",
"instances": [
{
"name": "x-axis",
"pins" : {
"stepgen_type": "step_dir_differential",
"step_pos_pin": "j3:6", "name": "_step_pos_pin",
"step_neg_pin": "j3:5", "name": "_step_neg_pin",
"dir_pos_pin": "j3:4", "name": "_dir_pos_pin",
"dir_neg_pin": "j3:2", "name": "_dir_neg_pin"
},
"soft_stop": true
...
} |
Thanks, but the code below doesn't work. TypeError: can only concatenate tuple (not "int") to tuple |
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Can you provide a stacktrace? Judging from the error, it originates from Python. Also, could you provide a |
root@debian:~# cat /etc/debian_version root@debian:~# python3 --version root@debian:~# pip freeze root@debian:~# cat /root/litex-cnc/emco5/emco5.json root@debian: |
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@Peter-van-Tol |
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I tried Debian 10 with Python 3.7 (installed today). |
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All tests are passing here (using the example as posted above). Is suspect an update somewhere, starting to update all packages. INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2023-06-04 19:27:27)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : LFE5U-25F-6BG256C.
INFO:SoC:System clock: 35.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU None added.
INFO:SoC:CPU None adding IO Region 0 at 0x00000000 (Size: 0x100000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False.
INFO:ECP5PLL:Creating ECP5PLL.
INFO:ECP5PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:ECP5PLL:Creating ClkOut0 sys of 35.00MHz (+-10000.00ppm).
INFO:ECP5PLL:Creating ClkOut1 sys_ps of 35.00MHz (+-10000.00ppm).
INFO:SoCBusHandler:master0 added as Bus Master.
INFO:ECP5PLL:Config:
clki_div : 1
clkfb : 2
clko0_freq : 35.00MHz
clko0_div : 15
clko0_phase: 0.00°
clko1_freq : 35.00MHz
clko1_div : 15
clko1_phase: 180.00°
clko2_div : 1
vco : 525.00MHz
clkfb_div : 21
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0x00000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectPointToPoint (1 <-> 1).
INFO:SoCCSRHandler:MMIO_inst CSR allocated at Location 0.
INFO:SoCCSRHandler:ctrl CSR allocated at Location 1.
INFO:SoCCSRHandler:ethphy CSR allocated at Location 2.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 3.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False
Bus Regions: (1)
csr : Origin: 0x00000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (1)
- master0
Bus Slaves: (1)
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (4)
- MMIO_inst : 0
- ctrl : 1
- ethphy : 2
- identifier_mem : 3
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO: Firmware created in test |
What Linux are you using? |
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Mij environment which I use to build the firmware is a Docker container: For reference, here is a list of packages installed ( The most obvious difference between the systems are the following entries:
however, I don't think it is due to one of these. I can see that you installed Litex-CNC from file, so I cannot verify of this installation has been correct and whether that version is up-to-date. The supported Python version are 3.8 to 3.10 (3.11 is untested so far), so it should not have been possible to install it on Debian 10 with Python 3.7 installed. Have to look into how |
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I tried at Xubuntu 20.04 (Python 3.8) and it doesn't work either. |
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I can understand the way you are feeling when things are not working. HOWEVER: the way you respond in this issue and the other issues is disrespectful in my opinion and does not reflect the willingness of others to help you with your problem. If you want to have all solutions handed over on a silver platter, please feel free to buy a commercial off the shelve product. |
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Side note on the error: This error is produced due to signed integers on the FPGA. It took a while to debug this problem, because it did not occur on all kernels. It did not occur on the WSL2 kernel I use for developing this project. Yesterday I finally received my RPi4 and moved development to that board (i.e. all test are now running on the Rpi4). Finally I could reproduce the error. It is solved in #11 |
I have LinuxCNC version 2.9 on Debian Bookworm, all (including LiteX-CNC) installed or compilled without warnings or errors.
Today I was try the 5a-75e-hello-gpio.json from examples.
I get:
user@debian:~/temp$ halrun -I test_gpio_blink.hal.
Note: Using POSIX realtime
litexcnc: Loading Litex CNC driver version 1.1.0
litexcnc: loading litexCNC etherbone driver version 0.02
litexcnc: Connecting to board at address: 192.168.0.99:1234.
litexcnc: Setting up modules...
litexcnc: - Watchdog
litexcnc: - Wallclock
litexcnc: - GPIO
litexcnc: - PWM
litexcnc: - Stepgen
litexcnc: - Encoder
litexcnc: Creating read and write buffers...
litexcnc: - Write buffer: 8 bytes)
litexcnc: - Read buffer: 16 bytes)
litexcnc: Exporting functions...
test_gpio_blink.hal:14: Pin 'test_PWM_GPIO.gpio.j1:1.out' does not exist
halcmd:.
I have no idea what happened...
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