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Verilog inline #279

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merged 3 commits into from
Sep 7, 2018
Merged

Verilog inline #279

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a76b492
added optional inlining for verilog
rdaly525 Aug 22, 2018
248c510
Make coreir-verilog inline a generic option
rsetaluri Sep 7, 2018
43f01e1
Refactor verilog inlining check
rsetaluri Sep 7, 2018
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2 changes: 2 additions & 0 deletions magma/compile.py
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Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,8 @@ def __compile_to_coreir(main, file_name, opts):
cmd += f" -o \"{split}/*.v\" -s"
else:
cmd += f" -o {file_name}.v"
if "inline" in opts and opts["inline"]:
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cmd += " --inline"
subprocess.run(cmd, shell=True)


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