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Verilog inline #279

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merged 3 commits into from Sep 7, 2018
Merged

Verilog inline #279

merged 3 commits into from Sep 7, 2018

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rsetaluri
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Make inlining verilog (through coreir) an option that can be specified.

rdaly525 and others added 2 commits September 6, 2018 23:48
Making inline verilog through coreir an option, rather than its own
compilation target.
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coveralls commented Sep 7, 2018

Pull Request Test Coverage Report for Build 1079

  • 0 of 2 (0.0%) changed or added relevant lines in 1 file are covered.
  • 1 unchanged line in 1 file lost coverage.
  • Overall coverage decreased (-0.03%) to 70.43%

Changes Missing Coverage Covered Lines Changed/Added Lines %
magma/compile.py 0 2 0.0%
Files with Coverage Reduction New Missed Lines %
magma/compile.py 1 72.62%
Totals Coverage Status
Change from base Build 1072: -0.03%
Covered Lines: 3344
Relevant Lines: 4748

💛 - Coveralls

magma/compile.py Outdated Show resolved Hide resolved
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@leonardt leonardt left a comment

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Looks good.

@leonardt leonardt merged commit 1c99426 into master Sep 7, 2018
@leonardt leonardt deleted the verilog_inline branch September 7, 2018 21:12
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4 participants