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fixed issues with synthesis: array width of axi ext mst/slv ports, ma…
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…cros for defines in one only line, opentitan defines for sim and carfield_pkg numMaster
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Maicol Ciani committed Apr 26, 2023
1 parent 1a0aec3 commit 5488280
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4 changes: 2 additions & 2 deletions Bender.lock
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Expand Up @@ -306,10 +306,10 @@ packages:
dependencies:
- common_cells
opentitan:
revision: 78e94cf76c133e4426f99c9bb32c5f7c929f13d0
revision: null
version: null
source:
Git: https://github.com/alsaqr-platform/opentitan.git
Path: working_dir/opentitan
dependencies:
- axi
- common_pads
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -15,7 +15,7 @@ dependencies:
car_l2: { git: git@iis-git.ee.ethz.ch:carfield/carfield_l2_mem.git, rev: cb2ba8146ca6b136b0e7b81884eb17c72a5d0ec2 } # branch: yt/carfield-integration
safety_island: { git: git@iis-git.ee.ethz.ch:carfield/safety-island.git, rev: 170649965a44b5c66c1c1670664b97b8e78bacb5 } # branch: master
pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 4f415e06d353ff97c225071e2dfa58a5cdd6b8ec } # branch: yt/carfield-integration
opentitan: { git: https://github.com/alsaqr-platform/opentitan.git, rev: 78e94cf76c133e4426f99c9bb32c5f7c929f13d0 } # branch: lowRISC-rebase
opentitan: { git: https://github.com/alsaqr-platform/opentitan.git, rev: f5274cdc90c1d1468a4285bae439cedfd8a02682 } # branch: lowRISC-rebase
mailbox_unit: { git: git@github.com:pulp-platform/mailbox_unit.git, rev: ce0cb2e7fe48a00fd2ee8b39f675e6c33a5a31d2 } # branch: aottaviano/mailbox-old

workspace:
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86 changes: 36 additions & 50 deletions hw/carfield.sv
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Expand Up @@ -17,9 +17,9 @@ module carfield
parameter cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault,
parameter int unsigned HypNumPhys = 1,
parameter int unsigned HypNumChips = 1,
parameter string RomCtrlBootRomInitFile = "",
parameter string OtpCtrlMemInitFile = "",
parameter string FlashCtrlMemInitFile = ""
parameter RomCtrlBootRomInitFile = "",

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[verible-verilog-lint] hw/carfield.sv#L20 

Explicitly define a storage type for every parameter and localparam, (RomCtrlBootRomInitFile). [Style: constants] [explicit-parameter-storage-type]
Raw output 
message:"Explicitly define a storage type for every parameter and localparam, (RomCtrlBootRomInitFile). [Style: constants] [explicit-parameter-storage-type]"  location:{path:"hw/carfield.sv"  range:{start:{line:20  column:13}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
parameter OtpCtrlMemInitFile = "",

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[verible-verilog-lint] hw/carfield.sv#L21 

Explicitly define a storage type for every parameter and localparam, (OtpCtrlMemInitFile). [Style: constants] [explicit-parameter-storage-type]
Raw output 
message:"Explicitly define a storage type for every parameter and localparam, (OtpCtrlMemInitFile). [Style: constants] [explicit-parameter-storage-type]"  location:{path:"hw/carfield.sv"  range:{start:{line:21  column:13}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
parameter FlashCtrlMemInitFile = ""

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[verible-verilog-lint] hw/carfield.sv#L22 

Explicitly define a storage type for every parameter and localparam, (FlashCtrlMemInitFile). [Style: constants] [explicit-parameter-storage-type]
Raw output 
message:"Explicitly define a storage type for every parameter and localparam, (FlashCtrlMemInitFile). [Style: constants] [explicit-parameter-storage-type]"  location:{path:"hw/carfield.sv"  range:{start:{line:22  column:13}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -190,24 +190,10 @@ localparam int unsigned IntClusterAxiMstRWidth =
Cfg.AxiUserWidth );

// Slave Side
`AXI_TYPEDEF_ALL_CT(axi_intcluster_slv ,
axi_intcluster_slv_req_t ,
axi_intcluster_slv_rsp_t ,
logic [Cfg.AddrWidth-1:0] ,
logic [IntClusterAxiIdInWidth-1:0],
logic [Cfg.AxiDataWidth-1:0] ,
logic [(Cfg.AxiDataWidth)/8-1:0] ,
logic [Cfg.AxiUserWidth-1:0] )
`AXI_TYPEDEF_ALL_CT(axi_intcluster_slv, axi_intcluster_slv_req_t, axi_intcluster_slv_rsp_t, logic [Cfg.AddrWidth-1:0], logic [IntClusterAxiIdInWidth-1:0], logic [Cfg.AxiDataWidth-1:0], logic [(Cfg.AxiDataWidth)/8-1:0], logic [Cfg.AxiUserWidth-1:0] )

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[verible-verilog-lint] hw/carfield.sv#L193 

Line length exceeds max: 100; is: 249 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 249 [Style: line-length] [line-length]"  location:{path:"hw/carfield.sv"  range:{start:{line:193  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

// Master side
`AXI_TYPEDEF_ALL_CT(axi_intcluster_mst ,
axi_intcluster_mst_req_t ,
axi_intcluster_mst_rsp_t ,
logic [Cfg.AddrWidth-1:0] ,
logic [IntClusterAxiIdOutWidth-1:0],
logic [Cfg.AxiDataWidth-1:0] ,
logic [(Cfg.AxiDataWidth)/8-1:0] ,
logic [Cfg.AxiUserWidth-1:0] )
// Master side

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[verible-verilog-lint] hw/carfield.sv#L195 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/carfield.sv"  range:{start:{line:195  column:15}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:195  column:15}  end:{line:196}}  text:"// Master side\n"}
`AXI_TYPEDEF_ALL_CT(axi_intcluster_mst, axi_intcluster_mst_req_t, axi_intcluster_mst_rsp_t, logic [Cfg.AddrWidth-1:0], logic [IntClusterAxiIdOutWidth-1:0], logic [Cfg.AxiDataWidth-1:0], logic [(Cfg.AxiDataWidth)/8-1:0], logic [Cfg.AxiUserWidth-1:0] )

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[verible-verilog-lint] hw/carfield.sv#L196 

Line length exceeds max: 100; is: 250 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 250 [Style: line-length] [line-length]"  location:{path:"hw/carfield.sv"  range:{start:{line:196  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

// Local DRAM buses and parameter
carfield_axi_llc_req_t dram_req;
Expand Down Expand Up @@ -255,38 +241,38 @@ logic [ LogDepth:0] llc_w_wptr;
logic [ LogDepth:0] llc_w_rptr;

// All AXI Slaves (except the Integer Cluster)
logic [iomsb(Cfg.AxiExtNumSlv-1):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_aw_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_w_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_w_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_b_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_b_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_ar_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_ar_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_r_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_r_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_aw_rptr;
logic [iomsb(Cfg.AxiExtNumSlv):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_w_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_w_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_b_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_b_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_ar_wptr;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_ar_rptr;
logic [iomsb(Cfg.AxiExtNumSlv):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_r_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv):0][ LogDepth:0] axi_slv_ext_r_rptr ;

// All AXI Slaves (except the Integer Cluster)
logic [iomsb(Cfg.AxiExtNumMst-1):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_aw_rptr;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_w_wptr ;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_w_rptr ;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_b_wptr ;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_b_rptr ;
logic [iomsb(Cfg.AxiExtNumMst-1):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_ar_wptr;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_ar_rptr;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_r_wptr ;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_r_rptr ;
logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_rptr;
logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_wptr ;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_rptr ;
logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_wptr ;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_rptr ;
logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_wptr;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_rptr;
logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_wptr ;
logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_rptr ;

// Integer Cluster Slave Bus
logic [IntClusterAxiSlvAwWidth-1:0] axi_slv_intcluster_aw_data;
Expand Down
4 changes: 2 additions & 2 deletions hw/carfield_pkg.sv
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Expand Up @@ -48,8 +48,8 @@ typedef enum doub_bt {

// Ext Slaves: L2Ports + Safety Island + Integer Cluster + Security Island Mailbox
localparam bit [2:0] AxiNumExtSlv = 3'd2 + 3'd1 + 3'd1 + 3'd1;
// Ext Masters: Integer Cluster + Security Island
localparam bit [2:0] AxiNumExtMst = 3'd1 + 3'd1;
// Ext Masters: Integer Cluster + Security Island + Safety Island
localparam bit [2:0] AxiNumExtMst = 3'd1 + 3'd1 + 3'd1;
// Ext Interrupts: Security Island Mailbox
localparam bit [2:0] NumExtIntrs = 3'd1;

Expand Down
50 changes: 33 additions & 17 deletions hw/l2_wrapper.sv
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Expand Up @@ -17,6 +17,7 @@ module l2_wrapper
parameter int unsigned AxiDataWidth = 64,
parameter int unsigned AxiIdWidth = 5,
parameter int unsigned AxiUserWidth = 1,
parameter int unsigned AxiMaxTrans = 8,
parameter int unsigned LogDepth = 3,
/// Mapping rules
parameter int unsigned NumRules = car_l2_pkg::NUM_MAP_TYPES * NumPort,
Expand Down Expand Up @@ -46,7 +47,8 @@ module l2_wrapper
)(
input logic clk_i ,
input logic rst_ni ,
// Port 1
input logic [NumPort-1:0] axi_isolate_i ,
output logic [NumPort-1:0] axi_isolated_o ,
input logic [NumPort-1:0][ArWidth-1:0] slvport_ar_data_i,
input logic [NumPort-1:0][ LogDepth:0] slvport_ar_wptr_i,
output logic [NumPort-1:0][ LogDepth:0] slvport_ar_rptr_o,
Expand All @@ -65,17 +67,10 @@ module l2_wrapper
output logic ecc_error_o
);

`AXI_TYPEDEF_ALL_CT(axi_async ,
axi_async_req_t ,
axi_async_rsp_t ,
logic [AxiAddrWidth-1:0],
logic [ AxiIdWidth-1:0],
logic [AxiDataWidth-1:0],
logic [AxiStrbWidth-1:0],
logic [AxiUserWidth-1:0])
`AXI_TYPEDEF_ALL_CT(axi_async, axi_async_req_t, axi_async_rsp_t, logic [AxiAddrWidth-1:0], logic [ AxiIdWidth-1:0], logic [AxiDataWidth-1:0], logic [AxiStrbWidth-1:0], logic [AxiUserWidth-1:0])

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[verible-verilog-lint] hw/l2_wrapper.sv#L70 

Line length exceeds max: 100; is: 194 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 194 [Style: line-length] [line-length]"  location:{path:"hw/l2_wrapper.sv"  range:{start:{line:70  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

axi_async_req_t [NumPort-1:0] axi_async_req;
axi_async_rsp_t [NumPort-1:0] axi_async_rsp;
axi_async_req_t [NumPort-1:0] axi_async_req, axi_isolate_req;
axi_async_rsp_t [NumPort-1:0] axi_async_rsp, axi_isolate_rsp;

for (genvar i = 0; i < NumPort; i++) begin: gen_cdc_fifos
axi_cdc_dst #(
Expand Down Expand Up @@ -110,6 +105,27 @@ for (genvar i = 0; i < NumPort; i++) begin: gen_cdc_fifos
.dst_req_o ( axi_async_req [i] ),
.dst_resp_i ( axi_async_rsp [i] )
);

axi_isolate #(
.NumPending ( AxiMaxTrans ),
.TerminateTransaction ( 1 ),
.AtopSupport ( 1 ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidth ( AxiIdWidth ),
.AxiUserWidth ( AxiUserWidth ),
.axi_req_t ( axi_async_req_t ),
.axi_resp_t ( axi_async_rsp_t )
) i_axi_slave_isolate (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slv_req_i ( axi_async_req[i] ),
.slv_resp_o ( axi_async_rsp[i] ),
.mst_req_o ( axi_isolate_req[i] ),
.mst_resp_i ( axi_isolate_rsp[i] ),
.isolate_i ( axi_isolate_i[i] ),
.isolated_o ( axi_isolated_o[i] )
);
end

typedef struct packed {
Expand Down Expand Up @@ -145,12 +161,12 @@ car_l2_top #(
.axi_req_t ( axi_async_req_t ),
.axi_resp_t ( axi_async_rsp_t )
) i_l2_top (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.mapping_rules_i ( mapping_rules ),
.axi_req_i ( axi_async_req ),
.axi_resp_o ( axi_async_rsp ),
.ecc_error_o ( ecc_error_o )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.mapping_rules_i ( mapping_rules ),
.axi_req_i ( axi_isolate_req ),
.axi_resp_o ( axi_isolate_rsp ),
.ecc_error_o ( ecc_error_o )
);

endmodule: l2_wrapper

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