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ci fix
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@chaoqun-liang
chaoqun-liang committed Jun 1, 2024
1 parent 8e0cd91 commit f990ced
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Showing 4 changed files with 58 additions and 65 deletions.
2 changes: 1 addition & 1 deletion hw/bootrom/cheshire_bootrom.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -2081,4 +2081,4 @@ module cheshire_bootrom #(
endcase
end

endmodule
endmodule
8 changes: 4 additions & 4 deletions hw/cheshire_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1353,7 +1353,7 @@ module cheshire_soc import cheshire_pkg::*; #(
);

eth_idma_wrap#(
.DataWidth ( Cfg.AxiDataWidth ),
.DataWidth ( Cfg.AxiDataWidth ),
.AddrWidth ( Cfg.AddrWidth ),
.UserWidth ( Cfg.AxiUserWidth ),
.AxiIdWidth ( Cfg.AxiMstIdWidth ),
Expand All @@ -1363,21 +1363,21 @@ module cheshire_soc import cheshire_pkg::*; #(
.reg_rsp_t ( reg_rsp_t )
) i_tx_eth_idma_wrap (
.clk_i,
.rst_ni,
.rst_ni,
.eth_clk_i ( eth_clk ),
.phy_rx_clk_i ( eth_rxck_i ),
.phy_rxd_i ( eth_rxd_i ),
.phy_rx_ctl_i ( eth_rxctl_i ),
.phy_tx_clk_o ( eth_txck_o ),
.phy_txd_o ( eth_txd_o ),
.phy_tx_ctl_o ( eth_txctl_o ),
.phy_resetn_o ( eth_rstn_o ),
.phy_resetn_o ( eth_rstn_o ),
.phy_intn_i ( 1'b1 ),
.phy_pme_i ( 1'b1 ),
.phy_mdio_i ( eth_mdio_i ),
.phy_mdio_o ( eth_mdio_o ),
.phy_mdio_oe ( eth_mdio_oe ),
.phy_mdc_o ( eth_mdc_o ),
.phy_mdc_o ( eth_mdc_o ),
.testmode_i ( testmode_i ),
.axi_req_o ( axi_in_req[AxiIn.eth] ),
.axi_rsp_i ( axi_in_rsp[AxiIn.eth] ),
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2 changes: 1 addition & 1 deletion hw/dma_core_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -355,4 +355,4 @@ module dma_core_wrap #(
.mst_resp_i ( axi_mst_rsp_i )
);

endmodule
endmodule
111 changes: 52 additions & 59 deletions sw/tests/ethernet.c
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Original file line number Diff line number Diff line change
Expand Up @@ -10,74 +10,67 @@
#include "printf.h"
#include "util.h"

#define ETH_BASE 0x0300c000
#define ETH_BASE 0x0300c000

#define MACLO_OFFSET 0x0
#define MACHI_OFFSET 0x4
#define IRQ_OFFSET 0x10
#define IDMA_SRC_ADDR_OFFSET 0x14
#define IDMA_DST_ADDR_OFFSET 0x18
#define IDMA_LENGTH_OFFSET 0x1c
#define IDMA_SRC_PROTO_OFFSET 0x20
#define IDMA_DST_PROTO_OFFSET 0x24
#define IDMA_REQ_VALID_OFFSET 0x3c
#define IDMA_REQ_READY_OFFSET 0x40
#define IDMA_RSP_READY_OFFSET 0x44
#define IDMA_RSP_VALID_OFFSET 0x48
#define MACLO_OFFSET 0x0
#define MACHI_OFFSET 0x4
#define IRQ_OFFSET 0x10
#define IDMA_SRC_ADDR_OFFSET 0x14
#define IDMA_DST_ADDR_OFFSET 0x18
#define IDMA_LENGTH_OFFSET 0x1c
#define IDMA_SRC_PROTO_OFFSET 0x20
#define IDMA_DST_PROTO_OFFSET 0x24
#define IDMA_REQ_VALID_OFFSET 0x3c
#define IDMA_REQ_READY_OFFSET 0x40
#define IDMA_RSP_READY_OFFSET 0x44
#define IDMA_RSP_VALID_OFFSET 0x48

#define PLIC_BASE 0x04000000
#define RV_PLIC_PRIO19_REG_OFFSET 0x4c
#define RV_PLIC_IE0_0_REG_OFFSET 0x2000
#define RV_PLIC_CC0_REG_OFFSET 0x200004
#define RV_PLIC_IE0_0_E_19_BIT 19
#define PLIC_ENABLE_REG_BASE PLIC_BASE + RV_PLIC_IE0_0_REG_OFFSET
#define PLIC_CLAIM_COMPLETE_BASE PLIC_BASE + RV_PLIC_CC0_REG_OFFSET
#define PLIC_BASE 0x04000000
#define RV_PLIC_PRIO19_REG_OFFSET 0x4c
#define RV_PLIC_IE0_0_REG_OFFSET 0x2000
#define RV_PLIC_CC0_REG_OFFSET 0x200004
#define RV_PLIC_IE0_0_E_19_BIT 19
#define PLIC_ENABLE_REG_BASE PLIC_BASE + RV_PLIC_IE0_0_REG_OFFSET
#define PLIC_CLAIM_COMPLETE_BASE PLIC_BASE + RV_PLIC_CC0_REG_OFFSET

#define RV_PLIC_IP_0_OFFSET 0x1000
#define RV_PLIC_IP_0_OFFSET 0x1000

#define PRINTF_ON

int main(void) {

#ifdef PRINTF_ON
printf ("Start test Ethernet...\n\r");
#endif
int main(void) {

*reg32(PLIC_BASE, RV_PLIC_PRIO19_REG_OFFSET) = 1;
*reg32(PLIC_BASE, RV_PLIC_IE0_0_REG_OFFSET) |= (1 << (RV_PLIC_IE0_0_E_19_BIT)); // Enable interrupt number ;
#ifdef PRINTF_ON
printf("Start test Ethernet...\n\r");
#endif

volatile uint64_t data_to_write[8] = {
0x1032207098001032,
0x3210E20020709800,
0x1716151413121110,
0x2726252423222120,
0x3736353433323130,
0x4746454443424140,
0x5756555453525150,
0x6766656463626160
};
*reg32(PLIC_BASE, RV_PLIC_PRIO19_REG_OFFSET) = 1;
*reg32(PLIC_BASE, RV_PLIC_IE0_0_REG_OFFSET) |=
(1 << (RV_PLIC_IE0_0_E_19_BIT)); // Enable interrupt number ;

// load data into mem
for (int i = 0; i < 8; ++i) {
volatile uint64_t *tx_addr = (volatile uint64_t*)(0x14000000 + i * sizeof(uint64_t));
volatile uint64_t data_to_write[8] = {
0x1032207098001032, 0x3210E20020709800, 0x1716151413121110, 0x2726252423222120,
0x3736353433323130, 0x4746454443424140, 0x5756555453525150, 0x6766656463626160};

// load data into mem
for (int i = 0; i < 8; ++i) {
volatile uint64_t *tx_addr = (volatile uint64_t *)(0x14000000 + i * sizeof(uint64_t));
*tx_addr = data_to_write[i];
}

*reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032;
*reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070;
}

*reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032;
*reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070;
*reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x14000000;
*reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = 0x0;
*reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = 0x40;
*reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x0;
*reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x5;

*reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
*reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0;
*reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1;

*reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = 0x14000000;
*reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET) = 0x0;
*reg32(ETH_BASE, IDMA_LENGTH_OFFSET) = 0x40;
*reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x0;
*reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x5;

*reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
*reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0;
*reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1;
while (!((*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19)));

while (!((*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ));

printf ("Ethernet test pass...\n\r");
return 0;
}
printf("Ethernet test pass...\n\r");
return 0;
}

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