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acc_dispatcher: Unify with CVXIF
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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@niwis
niwis committed Jun 20, 2023
1 parent 3218daf commit abcaf83
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Showing 4 changed files with 87 additions and 63 deletions.
1 change: 1 addition & 0 deletions Bender.yml
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Expand Up @@ -85,6 +85,7 @@ sources:
- core/include/wt_cache_pkg.sv
- core/include/std_cache_pkg.sv
- core/include/axi_intf.sv
- core/include/acc_pkg.sv

# for all the below files use Flist.cva6 as baseline and also look at Makefile pd/synth

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32 changes: 13 additions & 19 deletions core/acc_dispatcher.sv
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Expand Up @@ -42,12 +42,8 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; (
input logic flush_unissued_instr_i,
input logic flush_ex_i,
// Accelerator interface
output accelerator_req_t acc_req_o,
output logic acc_req_valid_o,
input logic acc_req_ready_i,
input accelerator_resp_t acc_resp_i,
input logic acc_resp_valid_i,
output logic acc_resp_ready_o
output acc_pkg::accelerator_req_t acc_req_o,
input acc_pkg::accelerator_resp_t acc_resp_i
);

`include "common_cells/registers.svh"
Expand Down Expand Up @@ -128,7 +124,7 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; (
end

// An accelerator instruction was issued.
if (acc_req_valid_o)
if (acc_req_o.req_valid)
insn_ready_d[acc_req_o.trans_id] = 1'b0;
end: p_non_speculative_ff

Expand All @@ -152,18 +148,16 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; (
.valid_i (acc_req_valid ),
.ready_o (acc_req_ready ),
.data_o (acc_req_int ),
.valid_o (acc_req_valid_o),
.ready_i (acc_req_ready_i)
.valid_o (acc_req_o.req_valid),
.ready_i (acc_resp_i.req_ready)
);

assign acc_req_o = '{
insn : acc_req_int.insn,
rs1 : acc_req_int.rs1,
rs2 : acc_req_int.rs2,
frm : acc_req_int.frm,
trans_id : acc_req_int.trans_id,
store_pending: !acc_no_st_pending_i && acc_cons_en_i
};
assign acc_req_o.insn = acc_req_int.insn;
assign acc_req_o.rs1 = acc_req_int.rs1;
assign acc_req_o.rs2 = acc_req_int.rs2;
assign acc_req_o.frm = acc_req_int.frm;
assign acc_req_o.trans_id = acc_req_int.trans_id;
assign acc_req_o.store_pending = !acc_no_st_pending_i && acc_cons_en_i;

always_comb begin: accelerator_req_dispatcher
// Do not fetch from the instruction queue
Expand Down Expand Up @@ -202,14 +196,14 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; (
// Unpack the accelerator response
assign acc_trans_id_o = acc_resp_i.trans_id;
assign acc_result_o = acc_resp_i.result;
assign acc_valid_o = acc_resp_valid_i;
assign acc_valid_o = acc_resp_i.resp_valid;
assign acc_exception_o = '{
cause: riscv::ILLEGAL_INSTR,
tval : '0,
valid: acc_resp_i.error
};
// Always ready to receive responses
assign acc_resp_ready_o = 1'b1;
assign acc_req_o.resp_ready = 1'b1;

// Signal dispatched load/store to issue stage
assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
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74 changes: 30 additions & 44 deletions core/cva6.sv
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Expand Up @@ -15,6 +15,8 @@

module cva6 import ariane_pkg::*; #(
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
parameter type cvxif_req_t = cvxif_pkg::cvxif_req_t,
parameter type cvxif_resp_t = cvxif_pkg::cvxif_resp_t,
parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth,
parameter int unsigned AxiDataWidth = ariane_axi::DataWidth,
parameter int unsigned AxiIdWidth = ariane_axi::IdWidth,
Expand All @@ -37,14 +39,6 @@ module cva6 import ariane_pkg::*; #(
input logic time_irq_i, // timer interrupt in (async)
input logic debug_req_i, // debug request (async)
`ifdef ARIANE_ACCELERATOR_PORT
// Accelerator request port
output accelerator_req_t acc_req_o,
output logic acc_req_valid_o,
input logic acc_req_ready_i,
// Accelerator response port
input accelerator_resp_t acc_resp_i,
input logic acc_resp_valid_i,
output logic acc_resp_ready_o,
// Invalidation requests
output logic acc_cons_en_o,
input logic [63:0] inval_addr_i,
Expand All @@ -54,8 +48,8 @@ module cva6 import ariane_pkg::*; #(
// RISC-V formal interface port (`rvfi`):
// Can be left open when formal tracing is not needed.
output ariane_pkg::rvfi_port_t rvfi_o,
output cvxif_pkg::cvxif_req_t cvxif_req_o,
input cvxif_pkg::cvxif_resp_t cvxif_resp_i,
output cvxif_req_t cvxif_req_o,
input cvxif_resp_t cvxif_resp_i,
// L15 (memory side)
output wt_cache_pkg::l15_req_t l15_req_o,
input wt_cache_pkg::l15_rtrn_t l15_rtrn_i,
Expand All @@ -76,6 +70,8 @@ module cva6 import ariane_pkg::*; #(
logic [NR_COMMIT_PORTS-1:0] commit_ack;

localparam NumPorts = 3;
cvxif_pkg::cvxif_req_t cvxif_req;
cvxif_pkg::cvxif_resp_t cvxif_resp;

// --------------
// PCGEN <-> CSR
Expand Down Expand Up @@ -153,6 +149,8 @@ module cva6 import ariane_pkg::*; #(
logic acc_valid_ex_id;
exception_t acc_exception_ex_id;
logic halt_acc_ctrl;
logic [4:0] acc_resp_fflags;
logic acc_resp_fflags_valid;
// CSR
logic csr_valid_id_ex;
// CVXIF
Expand Down Expand Up @@ -285,36 +283,20 @@ module cva6 import ariane_pkg::*; #(
logic [ariane_pkg::TRANS_ID_BITS-1:0] lsu_addr_trans_id;

// Accelerator port
accelerator_req_t acc_req;
logic acc_req_valid;
logic acc_req_ready;
accelerator_resp_t acc_resp;
logic acc_resp_valid;
logic acc_resp_ready;
logic [63:0] inval_addr;
logic inval_valid;
logic inval_ready;

`ifdef ARIANE_ACCELERATOR_PORT
assign acc_req_o = acc_req;
assign acc_req_valid_o = acc_req_valid;
assign acc_req_ready = acc_req_ready_i;
assign acc_resp = acc_resp_i;
assign acc_resp_valid = acc_resp_valid_i;
assign acc_resp_ready_o = acc_resp_ready;
assign inval_addr = inval_addr_i;
assign inval_valid = inval_valid_i;
assign inval_ready_o = inval_ready;
assign acc_cons_en_o = acc_cons_en_csr;
`else
assign acc_req_ready = '0;
assign acc_resp = '0;
assign acc_resp_valid = '0;
assign inval_addr = '0;
assign inval_valid = '0;
`endif


// --------------
// Frontend
// --------------
Expand Down Expand Up @@ -549,8 +531,8 @@ module cva6 import ariane_pkg::*; #(
.x_result_o ( x_result_ex_id ),
.x_valid_o ( x_valid_ex_id ),
.x_we_o ( x_we_ex_id ),
.cvxif_req_o ( cvxif_req_o ),
.cvxif_resp_i ( cvxif_resp_i ),
.cvxif_req_o ( cvxif_req ),
.cvxif_resp_i ( cvxif_resp ),
// Accelerator
.acc_valid_i ( acc_valid_acc_ex ),
// Performance counters
Expand Down Expand Up @@ -659,8 +641,8 @@ module cva6 import ariane_pkg::*; #(
.set_debug_pc_o ( set_debug_pc ),
.trap_vector_base_o ( trap_vector_base_commit_pcgen ),
.priv_lvl_o ( priv_lvl ),
.acc_fflags_ex_i ( acc_resp.fflags ),
.acc_fflags_ex_valid_i ( acc_resp.fflags_valid ),
.acc_fflags_ex_i ( acc_resp_fflags ),
.acc_fflags_ex_valid_i ( acc_resp_fflags_valid ),
.fs_o ( fs ),
.fflags_o ( fflags_csr_commit ),
.frm_o ( frm_csr_id_issue_ex ),
Expand Down Expand Up @@ -897,22 +879,26 @@ module cva6 import ariane_pkg::*; #(
.commit_ack_i ( commit_ack ),
.acc_no_st_pending_i ( no_st_pending_commit ),
.ctrl_halt_o ( halt_acc_ctrl ),
.acc_req_o ( acc_req ),
.acc_req_valid_o ( acc_req_valid ),
.acc_req_ready_i ( acc_req_ready_i ),
.acc_resp_i ( acc_resp_i ),
.acc_resp_valid_i ( acc_resp_valid_i ),
.acc_resp_ready_o ( acc_resp_ready )
.acc_req_o ( cvxif_req_o ),
.acc_resp_i ( cvxif_resp_i )
);

assign acc_resp_fflags = cvxif_resp_i.fflags;
assign acc_resp_fflags_valid = cvxif_resp_i.fflags_valid;

// Tie off cvxif
assign cvxif_resp = '0;
end : gen_accelerator else begin: gen_no_accelerator
assign acc_req = '0;
assign acc_req_valid = 1'b0;
assign acc_resp_ready = 1'b0;

assign acc_trans_id_ex_id = '0;
assign acc_result_ex_id = '0;
assign acc_valid_ex_id = '0;
assign acc_exception_ex_id = '0;
assign acc_trans_id_ex_id = '0;
assign acc_result_ex_id = '0;
assign acc_valid_ex_id = '0;
assign acc_exception_ex_id = '0;
assign acc_resp_fflags = '0;
assign acc_resp_fflags_valid = '0;

// Feed through cvxif
assign cvxif_req_o = cvxif_req;
assign cvxif_resp = cvxif_resp_i;
end : gen_no_accelerator

// -------------------
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43 changes: 43 additions & 0 deletions core/include/acc_pkg.sv
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@@ -0,0 +1,43 @@
// Copyright 2023 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51

// Authors: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
// Nils Wistoff <nwistoff@iis.ee.ethz.ch>

// Package defining the accelerator interface as used by Ara + CVA6

package acc_pkg;

// ----------------------
// Accelerator Interface
// ----------------------

typedef struct packed {
logic req_valid;
logic resp_ready;
riscv::instruction_t insn;
riscv::xlen_t rs1;
riscv::xlen_t rs2;
fpnew_pkg::roundmode_e frm;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
logic store_pending;
} accelerator_req_t;

typedef struct packed {
logic req_ready;
logic resp_valid;
riscv::xlen_t result;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
logic error;

// Metadata
logic store_pending;
logic store_complete;
logic load_complete;

logic [4:0] fflags;
logic fflags_valid;
} accelerator_resp_t;

endpackage

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