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[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system (#106)
* [TeraPool] Configurations Changes for TeraPool merge into MemPool * [DRAMsys] add dram rtl model * [DRAMsys] fix simulation bug * [DRAMsys] setting to add dramsys support * [DRAMsys] fix bugs: stack overflow when reading from dramsys * [Software] Temp change for easy debug * [DMA] DMA bug fix and mempool trace bug fix * [DRAM] Update DRAM lib with AXI reordering * [DRAM] Format codes * [DRAM] Merge SRAM and DRAM simulation in one RTL file * [Software] Update memcpy kernel * [Makefile] Update Makefile control simulation with dram var * [DRAM] Delete old file * [Bender] Remove the deleted RTL file * [RTL] Change the AXI MUX to AXI Xbar to connect the DRAM * [DRAM] DRAM update to support interleaved address mapping * [DRAM] Update DRAM model to support interleaved mode and fix write bugs * [Hardware] Support the different interleave mode for DRAM access * [Config] L2 address and size update * [Kernel] memcpy kernel update * [DRAM] Non-Ideal PHY latency support * [DRAM] Python Script for DRAM Bandwidth Analysis * [Format] Format the files for CI check * [Format] Format and put liscenses to files for CI checking * [Format] Format DRAM python script for CI check * [AXI] Update Auto Spliter Adding, Update Interleave SystemVerilog Writing Style * [HBM2E] Update DRAM HBM model to MICRON HBM2E-3600 * [Env] Update some configurations, include the fifo size and DRAM configuration * [Rebase] Rebase the DRAM work on top of main branch * [Config] Complete MinPool config for CI checking * [memcpy] Reduce transfer size for MinPool CI check * [memcpy] Reduce transfer size for MinPool CI check * [memcpy] Remove unused dump from kernel * [FIFO depth] The Fifo depth tune for support 8 outstanding transctions to hide DRAM latency * [DRAMsys] Remove the local version of DRAMsys hardware folder, add the open-sourced DRAMsys as a submodule * [Config] Move the dram related configurations to the config.mk * [Makefile] Modify Makefile for updating submodule, patching dram configurations, and compiling dramsys dynamic library. * [hardware] hardware change for the new version dramsys support * [DRAM] Add the configuration files for HBM2 DRAM simulation, these file will patch to dram_sim_rtl submodule by makefile target * [tb] Change back the simulation clk period to 2ns, but 1ns will have better DRAM BW as the HBM2 support upto 3600Gbps DDR * [Bender] Update bender to the correct RTL name, as DRAMsys updated themself * [software] Update memcpy kernel with reasonable transfer size and turn on the verification * [config] Change simulation to SRAM as L2 for CI checking * [CI test] Fix tb whitespace tailing and change the bender to compile dramsys rtl only by vsim * [CHANGELOG and README] Add changelog and readme for DRAM co-simulation * [Compiler version] Remove the cmake and gcc version from Makefile and update the ci.yml * [rtl] As we solved the bug in DRAM reset, set the reset edge back to the original version * Change the memcpy result dump CSR and remove the repeat in Makefile --------- Co-authored-by: Zhang Chi <chizhang@iis.ee.ethz.ch>
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Submodule dram_rtl_sim
added at
15caf3
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Original file line number | Diff line number | Diff line change |
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{ | ||
"simulation": { | ||
"addressmapping": "am_hbm2e_16Gb_pc_brc.json", | ||
"mcconfig": "mc_hbm2e_fr_fcfs_grp.json", | ||
"memspec": "ms_hbm2e_16Gb_3600.json", | ||
"simconfig": "simconfig_hbm2e.json", | ||
"simulationid": "hbm2e", | ||
"tracesetup": [ | ||
{ | ||
"clkMhz": 1800, | ||
"name": "HBM2E.stl" | ||
} | ||
] | ||
} | ||
} |
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{ | ||
"addressmapping": { | ||
"BYTE_BIT": [ | ||
0, | ||
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], | ||
"COLUMN_BIT": [ | ||
3, | ||
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], | ||
"PSEUDOCHANNEL_BIT":[ | ||
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], | ||
"BANK_BIT": [ | ||
16, | ||
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], | ||
"BANKGROUP_BIT":[ | ||
6, | ||
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], | ||
"ROW_BIT": [ | ||
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] | ||
} | ||
} |
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{ | ||
"mcconfig": { | ||
"PagePolicy": "Open", | ||
"Scheduler": "FrFcfsGrp", | ||
"SchedulerBuffer": "Bankwise", | ||
"RequestBufferSize": 128, | ||
"CmdMux": "Oldest", | ||
"RespQueue": "Fifo", | ||
"RefreshPolicy": "AllBank", | ||
"RefreshMaxPostponed": 8, | ||
"RefreshMaxPulledin": 8, | ||
"PowerDownPolicy": "NoPowerDown", | ||
"Arbiter": "Simple", | ||
"PhyDelayFw": 8, | ||
"PhyDelayBw": 9, | ||
"ThinkDelayFw": 12, | ||
"ThinkDelayBW": 12, | ||
"MaxActiveTransactions": 128 | ||
} | ||
} |
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{ | ||
"memspec": { | ||
"memarchitecturespec": { | ||
"burstLength": 4, | ||
"dataRate": 2, | ||
"nbrOfBankGroups": 8, | ||
"nbrOfBanks": 32, | ||
"nbrOfColumns": 128, | ||
"nbrOfPseudoChannels": 2, | ||
"nbrOfRows": 32768, | ||
"width": 64, | ||
"nbrOfDevices": 1, | ||
"nbrOfChannels": 1 | ||
}, | ||
"memoryId": "Test MemPool-TeraPool with HBM2 upto 3600bps (16Gb, Single Channel)", | ||
"memoryType": "HBM2", | ||
"memtimingspec": { | ||
"CCDL": 4, | ||
"CCDS": 2, | ||
"CKE": 8, | ||
"DQSCK": 2, | ||
"FAW": 9, | ||
"PL": 2, | ||
"RAS": 30, | ||
"RC": 45, | ||
"RCDRD": 16, | ||
"RCDWR": 12, | ||
"REFI": 3900, | ||
"REFISB": 122, | ||
"RFC": 260, | ||
"RFCSB": 200, | ||
"RL": 41, | ||
"RP": 15, | ||
"RRDL": 2.22, | ||
"RRDS": 2.22, | ||
"RREFD": 8, | ||
"RTP": 4, | ||
"RTW": 18, | ||
"WL": 8, | ||
"WR": 41, | ||
"WTRL": 6, | ||
"WTRS": 4, | ||
"XP": 10, | ||
"XS": 270, | ||
"clkMhz": 1800 | ||
} | ||
} | ||
} |
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