[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system #106

yichao-zh · 2024-03-22T09:56:51Z

Continuation of #93:

Changelog

Add DRAMsys co-simulation supporting

Added

Add dram_rtl_sim submodule for off-chip DRAM simulation
Add HBM2 DRAM configurations

Changed

mempool_tb hardware testbench with DRAM pre-loading function
memcpy kernel update with verification
mempool_system RTL update for DRAM interconnection
Makefile update for building the DRAMsys environment
README and CHANGELOG

Checklist

Automated tests pass
Changelog updated
Code style guideline is observed

SamuelRiedel

Thanks Yichao. I have a few questions and comments left. Also, just for the final PR, can we squash the commits that added and then removed the complete dram-sys dependency? Otherwise, they will always be in the main tree and add a significant overhead for every clone.

Makefile

config/mempool.mk

config/minpool.mk

config/terapool.mk

hardware/Makefile

hardware/src/mempool_cc.sv

Makefile

…ting Style

…iguration

…s to hide DRAM latency

…e open-sourced DRAMsys as a submodule

…igurations, and compiling dramsys dynamic library.

…le will patch to dram_sim_rtl submodule by makefile target

…better DRAM BW as the HBM2 support upto 3600Gbps DDR

…emself

…n on the verification

…dramsys rtl only by vsim

… update the ci.yml

…the original version

SamuelRiedel

LGTM. Thanks a lot :)

config/mempool.mk

hardware/Makefile

yichao-zh self-assigned this Mar 22, 2024

yichao-zh requested review from SamuelRiedel, mbertuletti and sermazz as code owners March 22, 2024 09:56

SamuelRiedel reviewed Apr 23, 2024

View reviewed changes

yichao-zh and others added 25 commits May 2, 2024 14:45

[TeraPool] Configurations Changes for TeraPool merge into MemPool

8dadebb

[DRAMsys] add dram rtl model

6e8372f

[DRAMsys] fix simulation bug

c3f4193

[DRAMsys] setting to add dramsys support

ed094fc

[DRAMsys] fix bugs: stack overflow when reading from dramsys

8aad3cf

[Software] Temp change for easy debug

0ad8fed

[DMA] DMA bug fix and mempool trace bug fix

cc207b5

[DRAM] Update DRAM lib with AXI reordering

9af009c

[DRAM] Format codes

f4429c5

[DRAM] Merge SRAM and DRAM simulation in one RTL file

07fc5c1

[Software] Update memcpy kernel

f5c0f70

[Makefile] Update Makefile control simulation with dram var

0d34a3a

[DRAM] Delete old file

3f8fb45

[Bender] Remove the deleted RTL file

d0c392f

[RTL] Change the AXI MUX to AXI Xbar to connect the DRAM

9a66177

[DRAM] DRAM update to support interleaved address mapping

90994c6

[DRAM] Update DRAM model to support interleaved mode and fix write bugs

8477c3e

[Hardware] Support the different interleave mode for DRAM access

2b1823e

[Config] L2 address and size update

dd31fc7

[Kernel] memcpy kernel update

33d5ceb

[DRAM] Non-Ideal PHY latency support

d340df8

[DRAM] Python Script for DRAM Bandwidth Analysis

f5ddb03

[Format] Format the files for CI check

5cd074f

[Format] Format and put liscenses to files for CI checking

6982eee

[Format] Format DRAM python script for CI check

b21d3a1

yichao-zh added 21 commits May 2, 2024 14:48

[AXI] Update Auto Spliter Adding, Update Interleave SystemVerilog Wri…

21995f9

…ting Style

[HBM2E] Update DRAM HBM model to MICRON HBM2E-3600

2f08548

[Env] Update some configurations, include the fifo size and DRAM conf…

71ac640

…iguration

[Rebase] Rebase the DRAM work on top of main branch

1b5ca59

[Config] Complete MinPool config for CI checking

19d0a0b

[memcpy] Reduce transfer size for MinPool CI check

330a61c

[memcpy] Reduce transfer size for MinPool CI check

d4895e1

[memcpy] Remove unused dump from kernel

7e8212b

[FIFO depth] The Fifo depth tune for support 8 outstanding transction…

6e320aa

…s to hide DRAM latency

[DRAMsys] Remove the local version of DRAMsys hardware folder, add th…

943c0bc

…e open-sourced DRAMsys as a submodule

[Config] Move the dram related configurations to the config.mk

d353685

[Makefile] Modify Makefile for updating submodule, patching dram conf…

ec56074

…igurations, and compiling dramsys dynamic library.

[hardware] hardware change for the new version dramsys support

037984f

[DRAM] Add the configuration files for HBM2 DRAM simulation, these fi…

46f4774

…le will patch to dram_sim_rtl submodule by makefile target

[tb] Change back the simulation clk period to 2ns, but 1ns will have …

c7a2faf

…better DRAM BW as the HBM2 support upto 3600Gbps DDR

[Bender] Update bender to the correct RTL name, as DRAMsys updated th…

6652780

…emself

[software] Update memcpy kernel with reasonable transfer size and tur…

6e6fd87

…n on the verification

[config] Change simulation to SRAM as L2 for CI checking

058dc2a

[CI test] Fix tb whitespace tailing and change the bender to compile …

fc2fcdb

…dramsys rtl only by vsim

[CHANGELOG and README] Add changelog and readme for DRAM co-simulation

89d7e74

[Compiler version] Remove the cmake and gcc version from Makefile and…

92891f6

… update the ci.yml

yichao-zh force-pushed the terapool_DRAM_RTL branch 2 times, most recently from 6ab46ef to 92891f6 Compare May 2, 2024 16:53

[rtl] As we solved the bug in DRAM reset, set the reset edge back to …

d4b06f2

…the original version

yichao-zh requested a review from SamuelRiedel May 2, 2024 17:22

Change the memcpy result dump CSR and remove the repeat in Makefile

63b3b25

SamuelRiedel approved these changes May 3, 2024

View reviewed changes

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yichao-zh merged commit 9dd79af into main May 6, 2024
58 checks passed

yichao-zh deleted the terapool_DRAM_RTL branch May 6, 2024 11:49

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[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system #106

[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system #106

yichao-zh commented Mar 22, 2024 •

edited by SamuelRiedel

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[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system #106

[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system #106

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yichao-zh commented Mar 22, 2024 • edited by SamuelRiedel Loading

Changelog

Added

Changed

Checklist

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yichao-zh commented Mar 22, 2024 •

edited by SamuelRiedel

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