Merge pull request #70 from emmicro-us/fix-be-on-read

Fix for SBA 'be' when reading (fixes #22).
pulp-platform · Jul 23, 2020 · a29af9e · a29af9e
2 parents 834853c + 08c6819
commit a29af9e
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Showing 3 changed files with 31 additions and 18 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ## [Unreleased]
 
 ### Added
+- Added parameter ReadByteEnable that may be disabled to revert SBA _be_ behavior to 0 on reads
 - Optional wrapper `dm_obi_top.sv` that wraps `dm_top` providing an OBI compliant interface
 - `tb` that runs dm in conjunction with ri5cy and OpenOCD
 - `.travis-ci.yml` running `tb` with verilator
@@ -15,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Made second scratch register optional (default is two) from [@zarubaf](https://github.com/zarubaf
 
 ### Fixed
+- Fix for SBA _be_ when reading to match the request size from [@jm4rtin](https://github.com/jm4rtin)
 - Off-by-one error in data and progbuf end address from [@pbing](https://github.com/pbing)
 - Haltsum1-3 calculation
 

diff --git a/src/dm_sba.sv b/src/dm_sba.sv
@@ -16,7 +16,8 @@
 *
 */
 module dm_sba #(
-  parameter int unsigned BusWidth = 32
+  parameter int unsigned BusWidth = 32,
+  parameter bit          ReadByteEnable = 1
 ) (
   input  logic                   clk_i,       // Clock
   input  logic                   rst_ni,
@@ -60,10 +61,31 @@ module dm_sba #(
   logic                          gnt;
   logic                          we;
   logic [BusWidth/8-1:0]         be;
+  logic [BusWidth/8-1:0]         be_mask;
   logic [$clog2(BusWidth/8)-1:0] be_idx;
 
   assign sbbusy_o = logic'(state_q != Idle);
 
+  always_comb begin : p_be_mask
+    be_mask = '0;
+
+    // generate byte enable mask
+    unique case (sbaccess_i)
+      3'b000: begin
+        be_mask[be_idx] = '1;
+      end
+      3'b001: begin
+        be_mask[int'({be_idx[$high(be_idx):1], 1'b0}) +: 2] = '1;
+      end
+      3'b010: begin
+        if (BusWidth == 32'd64) be_mask[int'({be_idx[$high(be_idx)], 2'b0}) +: 4] = '1;
+        else                    be_mask = '1;
+      end
+      3'b011: be_mask = '1;
+      default: ;
+    endcase
+  end
+
   always_comb begin : p_fsm
     req     = 1'b0;
     address = sbaddress_i;
@@ -89,27 +111,14 @@ module dm_sba #(
 
       Read: begin
         req = 1'b1;
+        if (ReadByteEnable) be = be_mask;
         if (gnt) state_d = WaitRead;
       end
 
       Write: begin
         req = 1'b1;
         we  = 1'b1;
-        // generate byte enable mask
-        unique case (sbaccess_i)
-          3'b000: begin
-            be[be_idx] = '1;
-          end
-          3'b001: begin
-            be[int'({be_idx[$high(be_idx):1], 1'b0}) +: 2] = '1;
-          end
-          3'b010: begin
-            if (BusWidth == 32'd64) be[int'({be_idx[$high(be_idx)], 2'b0}) +: 4] = '1;
-            else                    be = '1;
-          end
-          3'b011: be = '1;
-          default: ;
-        endcase
+        be = be_mask;
         if (gnt) state_d = WaitWrite;
       end
 

diff --git a/src/dm_top.sv b/src/dm_top.sv
@@ -23,7 +23,8 @@ module dm_top #(
   parameter int unsigned        DmBaseAddress    = 'h1000, // default to non-zero page
   // Bitmask to select physically available harts for systems
   // that don't use hart numbers in a contiguous fashion.
-  parameter logic [NrHarts-1:0] SelectableHarts  = {NrHarts{1'b1}}
+  parameter logic [NrHarts-1:0] SelectableHarts  = {NrHarts{1'b1}},
+  parameter bit                 ReadByteEnable   = 1 // toggle new behavior to drive master_be_o during a read
 ) (
   input  logic                  clk_i,       // clock
   input  logic                  rst_ni,      // asynchronous reset active low, connect PoR here, not the system reset
@@ -149,7 +150,8 @@ module dm_top #(
   );
 
   dm_sba #(
-    .BusWidth(BusWidth)
+    .BusWidth(BusWidth),
+    .ReadByteEnable(ReadByteEnable)
   ) i_dm_sba (
     .clk_i,
     .rst_ni,