Fix for issue #74; updates to use latest version of CV32E40P

[Silabs-ArjanB]

This pull requests addresses the following:

• Fix for issue Question about assertion in dm_top.sv #74
• Updates to make Debug Module testbench work together with most recent version of RI5CY/CV32E40P
• Updates to move non-RTL code out of RTL files

Note that the original `ifndef VERILATOR to guard assertions causes problems for synthesis tools. Either the synthesis tool would object against the assertions or you would have to define VERILATOR (both of which are not okay). Now binding the assertions to the RTL for a cleaner split between assertions and RTL. Also got rid of the #0 construct in the assertions as that was not a clean solution.

Signed-off-by: Arjan Bink Arjan.Bink@silabs.com

[zarubaf]

enum types should end in _e

[Silabs-ArjanB]

I added a new commit to fix the naming issue

[zarubaf]

I think you are just running into the define problem with your synthesis tool because the // pragma translate_off is missing. I would strongly recommend not pulling out the assertions as I don't see any benefit from it - on the contrary - for integration (where you usually don't bind the assertions) you are missing out on any checks.

[Silabs-ArjanB]

I think you are just running into the define problem with your synthesis tool because the // pragma translate_off is missing. I would strongly recommend not pulling out the assertions as I don't see any benefit from it - on the contrary - for integration (where you usually don't bind the assertions) you are missing out on any checks.

Not all tools use such pragmas. The only work-around we had was to define VERILATOR during ASIC and FPGA synthesis, which is really a hack. Other reason for putting the assertions outside is to get rid of define usage in RTL code and to offer a path for (later) converting to UVM style warnings/errors (as otherwise warnings/errors will go unnoticed in UVM simulations)

[bluewww]

LGTM.

I didn't have really good experience with bind and various eda tools, but If you think it makes future uvm support easier I can accept it.