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Question about assertion in dm_top.sv #74
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Silabs-ArjanB
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Oct 7, 2020
…E40P; moved assertions out of RTL to prevent issues with various tools (e.g. synthesis tools) Signed-off-by: Arjan Bink <Arjan.Bink@silabs.com>
bluewww
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Oct 26, 2020
Fix for issue #74; updates to use latest version of CV32E40P
Fixed in #82 |
imphil
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Feb 24, 2021
Update code from upstream repository https://github.com/pulp- platform/riscv-dbg to revision e67a0a79e9268c13c4232fc2887692404d75a069 * Bender.yml: Fix path to `one scratch` debug rom (Florian Zaruba) * Update CHANGELOG.md (bluew) * write CmdErrBusy to cmderr only if cmderr contains 0 (Tzachi Noy) * Fix for pulp-platform/riscv-dbg#81 and pulp-platform/riscv-dbg#91 (Arjan Bink) * Fix for issue pulp-platform/riscv-dbg#63 (Arjan Bink) * Fix for issue pulp-platform/riscv-dbg#77 and pulp-platform/riscv- dbg#88 (Arjan Bink) * Fixed enumeration name (Arjan Bink) * Fix for pulp-platform/riscv-dbg#69 (Arjan Bink) * Fixed verilator file list (Arjan Bink) * Fix for issue pulp-platform/riscv-dbg#74; updates to use latest version of CV32E40P; moved assertions out of RTL to prevent issues with various tools (e.g. synthesis tools) (Arjan Bink) * return CmdErrBusy if accessing data or progbuf while command was executing (Tzachi Noy) * Added missing input keyword (Arjan Bink) * Added changelog entry for SBA be fix. (John Eric Martin) * Correction to be_mask signal and added parameter ReadByteEnable to restore the old behavior if desired. (John Eric Martin) * add <WaitWriteValid> after <Write> in dmi_jtag state machine (Tzachi Noy) * Fix for SBA 'be' when reading (fixes pulp-platform/riscv-dbg#22). (John Eric Martin) Signed-off-by: Philipp Wagner <phw@lowrisc.org>
imphil
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Feb 25, 2021
Update code from upstream repository https://github.com/pulp- platform/riscv-dbg to revision e67a0a79e9268c13c4232fc2887692404d75a069 * Bender.yml: Fix path to `one scratch` debug rom (Florian Zaruba) * Update CHANGELOG.md (bluew) * write CmdErrBusy to cmderr only if cmderr contains 0 (Tzachi Noy) * Fix for pulp-platform/riscv-dbg#81 and pulp-platform/riscv-dbg#91 (Arjan Bink) * Fix for issue pulp-platform/riscv-dbg#63 (Arjan Bink) * Fix for issue pulp-platform/riscv-dbg#77 and pulp-platform/riscv- dbg#88 (Arjan Bink) * Fixed enumeration name (Arjan Bink) * Fix for pulp-platform/riscv-dbg#69 (Arjan Bink) * Fixed verilator file list (Arjan Bink) * Fix for issue pulp-platform/riscv-dbg#74; updates to use latest version of CV32E40P; moved assertions out of RTL to prevent issues with various tools (e.g. synthesis tools) (Arjan Bink) * return CmdErrBusy if accessing data or progbuf while command was executing (Tzachi Noy) * Added missing input keyword (Arjan Bink) * Added changelog entry for SBA be fix. (John Eric Martin) * Correction to be_mask signal and added parameter ReadByteEnable to restore the old behavior if desired. (John Eric Martin) * add <WaitWriteValid> after <Write> in dmi_jtag state machine (Tzachi Noy) * Fix for SBA 'be' when reading (fixes pulp-platform/riscv-dbg#22). (John Eric Martin) Signed-off-by: Philipp Wagner <phw@lowrisc.org>
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Hey!
I have question about assertion in
src/dm_top.sv
:and in testbench
riscv_dbg/tb/tb_test_env
is:so
hartinfo_i
is always 0 here, so this assert will call $fatal.The text was updated successfully, but these errors were encountered: