Customized port name mapping during import

[ptpan]

To perform arbitrary Verilog import, the current PyMTL implementation actually assumes the names of ports in the Placeholder component has to be the same as those in the top level Verilog module. This is obviously not a sound assumption and a better approach (which pymtl v2 does) is to support a port name mapping between the python ports and the Verilog ports.

[ptpan]

Closed as #80 has been merged into master