3.0.0.dev0 with RAL UVM Register Access Layer

[raysalemi]

The UVM Register Access Layer (RAL) comes to pyuvm

pyuvm as I originally wrote it did not support the UVM Register Access Layer. Fortunately our wonderful contributors especially @EngRaff92 and @crteja took a leadership role in bringing RAL to pyuvm. This dev release is the first release of that work.

pyuvm* 3.0.0 will be the first RAL release. Before we make the release official, I am releasing this dev release so that people can try out the new technology.

Thank you to everyone who contributed to pyuvm 3.0.0.dev0!

Details and names are below.

What's Changed

• Automatic string conversion for log messages by @timothyscherer in Automatic string conversion for log messages #148
• Update example TinyALY to work with Verilator 5 by @teja-91 in Update example TinyALY to work with Verilator 5 #145
• Add support for uvm_transaction simulation time recording by @teja-91 in Add support for uvm_transaction simulation time recording #153
• Replace fork with start_soon in example by @crteja in Replace fork with start_soon in example #155
• Add implementation for chapter 17 by @crteja in Add implementation for chapter 17 #154
• Update uvm_reg_map implementation by @crteja in Update uvm_reg_map implementation #157
• Rationalized testing using tox by @raysalemi in Rationalized testing using tox #159
• Use 1800.2 naming convention for all base classes by @crteja in Use 1800.2 naming convention for all base classes #162
• Enable CI for ral_dev by @crteja in Enable CI for ral_dev #164
• TinyALU reg block implementation by @crteja in TinyALU reg block implementation #166
• PR branch to main shared ral_dev branch push by @EngRaff92 in PR branch to main shared ral_dev branch push #168
• Ral dev by @EngRaff92 in Ral dev #169
• Add the changes from PR 170 by @raysalemi in Add the changes from PR 170 #171
• Generate passthrough interface by @crteja in Generate passthrough interface #172
• Regenerate reg block using peakrdl-verilog by @crteja in Regenerate reg block using peakrdl-verilog #173
• Fix Replace fork with start_soon in tests.py #160, replace all cocotb.fork() with cocotb.start_soon() in all tests by @MehanathanS in Fix pyuvm#160, replace all cocotb.fork() with cocotb.start_soon() in all tests #175
• Fix Typo mentioned in Simple typo in Makefile #121 by @MehanathanS in Fix Typo mentioned in pyuvm#121 #176
• Add default argument to ConfigDB().get() by @timothyscherer in Add default argument to ConfigDB().get() #178
• Latest ral_dev update by @EngRaff92 in Latest ral_dev update #186
• Add RAL to pyuvm. This is the primary 3.0 feature by @raysalemi in Add RAL to pyuvm. This is the primary 3.0 feature #194

New Contributors

• @timothyscherer made their first contribution in Automatic string conversion for log messages #148
• @teja-91 made their first contribution in Update example TinyALY to work with Verilator 5 #145
• @crteja made their first contribution in Replace fork with start_soon in example #155
• @EngRaff92 made their first contribution in PR branch to main shared ral_dev branch push #168
• @MehanathanS made their first contribution in Fix pyuvm#160, replace all cocotb.fork() with cocotb.start_soon() in all tests #175

Full Changelog: 2.9.1...3.0.0.dev0

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This discussion was created from the release 3.0.0.dev0 with RAL UVM Register Access Layer.