Mirny CPLD gateware features

[jordens]

Hardware

https://github.com/sinara-hw/mirny/wiki

CPLD Gateware design

• SPI prefix-based based router (4 PLL, 4 ATT, 4 registers)
• Use only one CS, one EEM
• Independent access to RF switches as high resolution, high speed, contention-free RTIO TTL channels
• Configure RF switches via dedicated SPI register to allow saving RTIO/IO resources
• Read MUXOUT via EEM TTL RTIO (for precision timing measurements) or via SPI register
• IFC_MODE read-out
• Green LEDs driven from RF switches
• Red LEDs driven from !MUXOUT or bypassed
• Individual access to attenuators, not daisy-chained
• Fully configurable clocking, chip-enables, ATT reset, LVDS modes, MUXOUT routing modes
• Configurable mezzanine IO, bidirectional, GPIO register style, with option of routing 4 EEM IO to the mezzanine
• Documentation, flashing/deployment scripts

Status

This code and rudimentary ARTIQ coredevice support (without PLL register abstraction) are available for funding.

[jordens]

Current protocol and interface specification:

    Mirny IO router and configuration/status
    ========================================

    Pin Out
    -------

    | EEM LVDS pair | Function               |
    |---------------+------------------------|
    | EEM 0         | SCLK                   |
    | EEM 1         | MOSI                   |
    | EEM 2         | MISO, MUXOUT           |
    | EEM 3         | CS                     |
    | EEM 4         | SW0, MUXOUT0, MEZZ_IO0 |
    | EEM 5         | SW1, MUXOUT1, MEZZ_IO1 |
    | EEM 6         | SW2, MUXOUT2, MEZZ_IO2 |
    | EEM 7         | SW3, MUXOUT3, MEZZ_IO3 |

    SPI
    ---

    SPI xfer is ADR(7), WE(1), DAT(REG: 16, ATT: 8, PLL: 32)

    | ADR | TARGET |
    |--------+--------|
    | 0 | REG0     |
    | 1 | REG1     |
    | 2 | REG2     |
    | 3 | REG3     |
    | 4 | PLL0     |
    | 5 | PLL1     |
    | 6 | PLL2     |
    | 7 | PLL3     |
    | 8 | ATT0     |
    | 9 | ATT1     |
    | a | ATT2     |
    | b | ATT3     |
    | c | reserved |
    | d | reserved |
    | e | reserved |
    | f | reserved |

    The SPI interface is CPOL=0, CPHA=0, SPI mode 0, 4-wire, full fuplex.

    Configuration register

    The status bits are read on the falling edge of after the WE bit (8th
    falling edge).
    The configuration bits are updated at the last falling SCK edge of the SPI
    transaction (24th falling edge). The initial state is 0 (all bits cleared).
    The bits in the registers (from LSB to MSB) are:

    | Name      | Width | Function                           |
    |-----------+-------+------------------------------------|
    | HW_REV    | 2     | HW rev                             |
    | PROTO_REV | 2     | Protocol (see __proto_rev__)       |
    | IFC_MODE  | 4     | IFC_MODE[0:4]                      |
    | MUXOUT    | 4     | Muxout values                      |

    | Name      | Width | Function                           |
    |-----------+-------+------------------------------------|
    | CE_N      | 4     | PLL chip enable (bar)              |
    | CLK_SEL   | 2     | Selects CLK source: 0 OSC, 1 MMCX, |
    |           |       | 2 reserved, 3 SMA                  |
    | DIV       | 2     | Clock divider configuration:       |
    |           |       | 0: divide-by-one,                  |
    |           |       | 1: reserved,                       |
    |           |       | 2: divider-by-two,                 |
    |           |       | 3: divide-by-four                  |
    | ATT_RST   | 1     | Attenuator reset                   |
    | FSEN_N    | 1     | LVDS fail safe, Type 2 (bar)       |
    | MUXOUT_EEM| 1     | route MUXOUT to EEM[4:8]           |
    | EEM_MEZZIO| 1     | route EEM[4:8] to MEZZ_IO[0:4]     |

    | Name      | Width | Function                           |
    |-----------+-------+------------------------------------|
    | RF_SW     | 4     | RF switch state                    |

    | Name      | Width | Function                           |
    |-----------+-------+------------------------------------|
    | MEZZ_IO   | 8     | Mezzanine IO                       |
    | MEZZ_OE   | 8     | Mezzanine OE                       |

    Test points
    -----------

    The test points expose miscellaneous signals for debugging and are not part
    of the protocol revision.

[jordens]

Funded by LUH.

[jordens]

Gateware implemented in https://github.com/quartiq/mirny/tree/v0.2.4