Control Pounder through MQTT - finished

ad9959/src/lib.rs

@@ -2,8 +2,24 @@
 
 use bit_field::BitField;
 use bitflags::bitflags;
+use core::ops::Range;
 use embedded_hal::{blocking::delay::DelayUs, digital::v2::OutputPin};
 
+/// The minimum reference clock input frequency with REFCLK multiplier disabled.
+const MIN_REFCLK_FREQUENCY: f32 = 1e6;
+/// The minimum reference clock input frequency with REFCLK multiplier enabled.
+const MIN_MULTIPLIED_REFCLK_FREQUENCY: f32 = 10e6;
+/// The system clock frequency range with high gain configured for the internal VCO.
+const HIGH_GAIN_VCO_RANGE: Range<f32> = Range {
+    start: 255e6,
+    end: 500e6,
+};
+/// The system clock frequency range with low gain configured for the internal VCO.
+const LOW_GAIN_VCO_RANGE: Range<f32> = Range {
+    start: 100e6,
+    end: 160e6,
+};
+
 /// A device driver for the AD9959 direct digital synthesis (DDS) chip.
 ///
 /// This chip provides four independently controllable digital-to-analog output sinusoids with
@@ -216,23 +232,17 @@
         reference_clock_frequency: f32,
         multiplier: u8,
     ) -> Result<f32, Error> {
+        let frequency =
+            validate_clocking(reference_clock_frequency, multiplier)?;
         self.reference_clock_frequency = reference_clock_frequency;
 
-        if multiplier != 1 && !(4..=20).contains(&multiplier) {
-            return Err(Error::Bounds);
-        }
-
-        let frequency = multiplier as f32 * self.reference_clock_frequency;
-        if frequency > 500_000_000.0f32 {
-            return Err(Error::Frequency);
-        }
-
         // TODO: Update / disable any enabled channels?
         let mut fr1: [u8; 3] = [0, 0, 0];
         self.read(Register::FR1, &mut fr1)?;
         fr1[0].set_bits(2..=6, multiplier);
 
-        let vco_range = frequency > 255e6;
+        let vco_range = HIGH_GAIN_VCO_RANGE.contains(&frequency)
+            || frequency == HIGH_GAIN_VCO_RANGE.end;
         fr1[0].set_bit(7, vco_range);
 
         self.write(Register::FR1, &fr1)?;
@@ -363,9 +373,7 @@
         channel: Channel,
         phase_turns: f32,
     ) -> Result<f32, Error> {
-        let phase_offset: u16 =
-            (phase_turns * (1 << 14) as f32) as u16 & 0x3FFFu16;
-
+        let phase_offset = phase_to_pow(phase_turns)?;
         self.modify_channel(
             channel,
             Register::CPOW0,
@@ -511,6 +519,108 @@
     }
 }
 
+/// Validate the internal system clock configuration of the chip.
+///
+/// Arguments:
+/// * `reference_clock_frequency` - The reference clock frequency provided to the AD9959 core.
+/// * `multiplier` - The frequency multiplier of the system clock. Must be 1 or 4-20.
+///
+/// Returns:
+/// The system clock frequency to be configured.
+pub fn validate_clocking(
+    reference_clock_frequency: f32,
+    multiplier: u8,
+) -> Result<f32, Error> {
+    // The REFCLK frequency must be at least 1 MHz with REFCLK multiplier disabled.
+    if reference_clock_frequency < MIN_REFCLK_FREQUENCY {
+        return Err(Error::Bounds);
+    }
+    // If the REFCLK multiplier is enabled, the multiplier (FR1[22:18]) must be between 4 to 20.
+    // Alternatively, the clock multiplier can be disabled. The multiplication factor is 1.
+    if multiplier != 1 && !(4..=20).contains(&multiplier) {
+        return Err(Error::Bounds);
+    }
+    // If the REFCLK multiplier is enabled, the REFCLK frequency must be at least 10 MHz.
+    if multiplier != 1
+        && reference_clock_frequency < MIN_MULTIPLIED_REFCLK_FREQUENCY
+    {
+        return Err(Error::Bounds);
+    }
+    let frequency = multiplier as f32 * reference_clock_frequency;
+    // SYSCLK frequency between 255 MHz and 500 MHz (inclusive) is valid with high range VCO
+    if HIGH_GAIN_VCO_RANGE.contains(&frequency)
+        || frequency == HIGH_GAIN_VCO_RANGE.end
+    {
+        return Ok(frequency);
+    }
+
+    // SYSCLK frequency between 100 MHz and 160 MHz (inclusive) is valid with low range VCO
+    if LOW_GAIN_VCO_RANGE.contains(&frequency)
+        || frequency == LOW_GAIN_VCO_RANGE.end
+    {
+        return Ok(frequency);
+    }
+
+    // When the REFCLK multiplier is disabled, SYSCLK frequency can go below 100 MHz
+    if multiplier == 1 && (0.0..=LOW_GAIN_VCO_RANGE.start).contains(&frequency)
+    {
+        return Ok(frequency);
+    }
+
+    Err(Error::Frequency)
+}
+
+/// Convert and validate frequency into frequency tuning word.
+///
+/// Arguments:
+/// * `dds_frequency` - The DDS frequency to be converted and validated.
+/// * `system_clock_frequency` - The system clock frequency of the AD9959 core.
+///
+/// Returns:
+/// The corresponding frequency tuning word.
+pub fn frequency_to_ftw(
+    dds_frequency: f32,
+    system_clock_frequency: f32,
+) -> Result<u32, Error> {
+    // Output frequency should not exceed the Nyquist's frequency.
+    if !(0.0..=(system_clock_frequency / 2.0)).contains(&dds_frequency) {
+        return Err(Error::Bounds);
+    }
+    // The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the
+    // frequency tuning word and f_s is the system clock rate.
+    Ok(((dds_frequency / system_clock_frequency) * (1u64 << 32) as f32) as u32)
+}
+
+/// Convert phase into phase offset word.
+///
+/// Arguments:
+/// * `phase_turns` - The normalized number of phase turns of a DDS channel.
+///
+/// Returns:
+/// The corresponding phase offset word.
+pub fn phase_to_pow(phase_turns: f32) -> Result<u16, Error> {
+    Ok((phase_turns * (1 << 14) as f32) as u16 & 0x3FFFu16)
+}
+
+/// Convert amplitude into amplitude control register values.
+///
+/// Arguments:
+/// * `amplitude` - The normalized amplitude of a DDS channel.
+///
+/// Returns:
+/// The corresponding value in the amplitude control register.
+pub fn amplitude_to_acr(amplitude: f32) -> Result<u32, Error> {
+    if !(0.0..=1.0).contains(&amplitude) {
+        return Err(Error::Bounds);
+    }
+
+    let acr: u32 = *0u32
+        .set_bits(0..=9, ((amplitude * (1 << 10) as f32) as u32) & 0x3FF)
+        .set_bit(12, amplitude != 1.0);
+
+    Ok(acr as u32)
+}
+
 /// Represents a means of serializing a DDS profile for writing to a stream.
 pub struct ProfileSerializer {
     // heapless::Vec<u8, 32>, especially its extend_from_slice() is slow
@@ -566,6 +676,39 @@
         }
     }
 
+    /// Update the system clock configuration.
+    ///
+    /// # Args
+    /// * `reference_clock_frequency` - The reference clock frequency provided to the AD9959 core.
+    /// * `multiplier` - The frequency multiplier of the system clock. Must be 1 or 4-20.
+    ///
+    /// # Limitations
+    /// The correctness of the FR1 register setting code rely on FR1\[0:17\] staying 0.
+    pub fn set_system_clock(
+        &mut self,
+        reference_clock_frequency: f32,
+        multiplier: u8,
+    ) -> Result<f32, Error> {
+        let frequency = reference_clock_frequency * multiplier as f32;
+
+        // The enabled channel will be updated after clock reconfig
+        let mut fr1 = [0u8; 3];
+
+        // The ad9959 crate does not modify FR1[0:17]. These bits keep their default value.
+        // These bits by default are 0.
+        // Reading the register then update is not possible to implement in a serializer, where
+        // many QSPI writes are performed in burst. Switching between read and write requires
+        // breaking the QSPI indirect write mode and switch into the QSPI indirect read mode.
+        fr1[0].set_bits(2..=6, multiplier);
+
+        // Frequencies within the VCO forbidden range (160e6, 255e6) are already rejected.
+        let vco_range = HIGH_GAIN_VCO_RANGE.contains(&frequency);
+        fr1[0].set_bit(7, vco_range);
+
+        self.add_write(Register::FR1, &fr1);
+        Ok(frequency)
+    }
+
     /// Add a register write to the serialization data.
     fn add_write(&mut self, register: Register, value: &[u8]) {
         let data = &mut self.data[self.index..];

src/bin/dual-iir.rs

@@ -44,6 +44,8 @@ use stabilizer::{
         afe::Gain,
         dac::{Dac0Output, Dac1Output, DacCode},
         hal,
+        pounder::{ClockConfig, PounderConfig},
+        setup::PounderDevices as Pounder,
         signal_generator::{self, SignalGenerator},
         timers::SamplingTimer,
         DigitalInput0, DigitalInput1, SystemTimer, Systick, AFE0, AFE1,
@@ -145,6 +147,16 @@ pub struct Settings {
     /// See [signal_generator::BasicConfig#miniconf]
     #[miniconf(defer)]
     signal_generator: miniconf::Array<signal_generator::BasicConfig, 2>,
+
+    /// Specifies the config for pounder DDS clock configuration, DDS channels & attenuations
+    ///
+    /// # Path
+    /// `pounder`
+    ///
+    /// # Value
+    /// See [PounderConfig#miniconf]
+    #[miniconf(defer)]
+    pounder: miniconf::Option<PounderConfig>,
 }
 
 impl Default for Settings {
@@ -171,6 +183,8 @@ impl Default for Settings {
                 .into(),
 
             stream_target: StreamTarget::default(),
+
+            pounder: None.into(),
         }
     }
 }
@@ -189,6 +203,7 @@ mod app {
         settings: Settings,
         telemetry: TelemetryBuffer,
         signal_generator: [SignalGenerator; 2],
+        pounder: Option<Pounder>,
     }
 
     #[local]
@@ -199,6 +214,7 @@ mod app {
         adcs: (Adc0Input, Adc1Input),
         dacs: (Dac0Output, Dac1Output),
         iir_state: [[iir::Vec5<f32>; IIR_CASCADE_LENGTH]; 2],
+        dds_clock_state: Option<ClockConfig>,
         generator: FrameGenerator,
         cpu_temp_sensor: stabilizer::hardware::cpu_temp_sensor::CpuTempSensor,
     }
@@ -208,14 +224,21 @@ mod app {
         let clock = SystemTimer::new(|| monotonics::now().ticks() as u32);
 
         // Configure the microcontroller
-        let (stabilizer, _pounder) = hardware::setup::setup(
+        let (stabilizer, pounder) = hardware::setup::setup(
             c.core,
             c.device,
             clock,
             BATCH_SIZE,
             SAMPLE_TICKS,
         );
 
+        let dds_clock_state = pounder.as_ref().map(|_| ClockConfig::default());
+
+        let mut settings = Settings::default();
+        if pounder.is_some() {
+            settings.pounder.replace(PounderConfig::default());
+        }
+
         let mut network = NetworkUsers::new(
             stabilizer.net.stack,
             stabilizer.net.phy,
@@ -226,13 +249,12 @@ mod app {
                 .unwrap_or("10.34.16.1")
                 .parse()
                 .unwrap(),
+            settings,
         );
 
         let generator = network
             .configure_streaming(StreamFormat::AdcDacData, BATCH_SIZE as _);
 
-        let settings = Settings::default();
-
         let shared = Shared {
             network,
             settings,
@@ -249,6 +271,7 @@ mod app {
                         .unwrap(),
                 ),
             ],
+            pounder,
         };
 
         let mut local = Local {
@@ -258,6 +281,7 @@ mod app {
             adcs: stabilizer.adcs,
             dacs: stabilizer.dacs,
             iir_state: [[[0.; 5]; IIR_CASCADE_LENGTH]; 2],
+            dds_clock_state,
             generator,
             cpu_temp_sensor: stabilizer.temperature_sensor,
         };
@@ -407,7 +431,7 @@ mod app {
         }
     }
 
-    #[task(priority = 1, local=[afes], shared=[network, settings, signal_generator])]
+    #[task(priority = 1, local=[afes, dds_clock_state], shared=[network, settings, signal_generator, pounder])]
     fn settings_update(mut c: settings_update::Context) {
         let settings = c.shared.network.lock(|net| *net.miniconf.settings());
         c.shared.settings.lock(|current| *current = settings);
@@ -431,15 +455,28 @@ mod app {
             }
         }
 
+        // Update Pounder configurations
+        c.shared.pounder.lock(|pounder| {
+            if let Some(pounder) = pounder {
+                let pounder_settings = settings.pounder.as_ref().unwrap();
+                let mut clocking = c.local.dds_clock_state.unwrap();
+                pounder.update_dds(*pounder_settings, &mut clocking);
+            }
+        });
+
         let target = settings.stream_target.into();
         c.shared.network.lock(|net| net.direct_stream(target));
     }
 
-    #[task(priority = 1, shared=[network, settings, telemetry], local=[cpu_temp_sensor])]
+    #[task(priority = 1, shared=[network, settings, telemetry, pounder], local=[cpu_temp_sensor])]
     fn telemetry(mut c: telemetry::Context) {
         let telemetry: TelemetryBuffer =
             c.shared.telemetry.lock(|telemetry| *telemetry);
 
+        let pounder_telemetry = c.shared.pounder.lock(|pounder| {
+            pounder.as_mut().map(|pounder| pounder.get_telemetry())
+        });
+
         let (gains, telemetry_period) = c
             .shared
             .settings
@@ -450,6 +487,7 @@ mod app {
                 gains[0],
                 gains[1],
                 c.local.cpu_temp_sensor.get_temperature().unwrap(),
+                pounder_telemetry,
             ))
         });
 

src/bin/lockin.rs

@@ -254,6 +254,8 @@ mod app {
             SAMPLE_TICKS,
         );
 
+        let settings = Settings::default();
+
         let mut network = NetworkUsers::new(
             stabilizer.net.stack,
             stabilizer.net.phy,
@@ -264,6 +266,7 @@ mod app {
                 .unwrap_or("10.34.16.1")
                 .parse()
                 .unwrap(),
+            settings,
         );
 
         let generator = network
@@ -272,7 +275,7 @@ mod app {
         let shared = Shared {
             network,
             telemetry: TelemetryBuffer::default(),
-            settings: Settings::default(),
+            settings,
         };
 
         let signal_config = signal_generator::Config {
@@ -499,6 +502,7 @@ mod app {
                 gains[0],
                 gains[1],
                 c.local.cpu_temp_sensor.get_temperature().unwrap(),
+                None,
             ))
         });