Skip to content

Commit

Permalink
Merge pull request #262 from Radvall/add_flip_flops
Browse files Browse the repository at this point in the history 
Added spice entry for flip-flops
  • Loading branch information
@ra3xdh
ra3xdh committed Apr 21, 2023
2 parents adf3196 + 4ab7bc4 commit 7e2f2ab
Show file tree
Hide file tree
Showing 10 changed files with 331 additions and 6 deletions.
218 changes: 218 additions & 0 deletions examples/ngspice/flip_flops_truth_tables.sch
View file

Large diffs are not rendered by default.

29 changes: 28 additions & 1 deletion qucs/components/d_flipflop.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,10 +17,11 @@
#include "d_flipflop.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"

D_FlipFlop::D_FlipFlop()
{
Type = isDigitalComponent;
Type = isComponent;
Description = QObject::tr("D flip flop with asynchronous reset");

Props.append(new Property("t", "0", false, QObject::tr("delay time")));
Expand Down Expand Up @@ -52,6 +53,7 @@ D_FlipFlop::D_FlipFlop()
ty = y2+4;
Model = "DFF";
Name = "Y";
SpiceModel = "A";
}

// -------------------------------------------------------
Expand Down Expand Up @@ -119,3 +121,28 @@ Element* D_FlipFlop::info(QString& Name, char* &BitmapFile, bool getNewOne)
if(getNewOne) return new D_FlipFlop();
return 0;
}

QString D_FlipFlop::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");

QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("t")->Value);

QString SET = "0";
QString QB = "QB_" + Name;
QString D = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
QString CLK = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
QString Q = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);

s += " " + D + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;

s += " " + tmp_model + "\n";
s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
.arg(tmp_model).arg(td);
s += QString("C%1 QB_%1 0 1e-9 \n").arg(Name); // capacitor load for unused QB pin

return s;
}
1 change: 1 addition & 0 deletions qucs/components/d_flipflop.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@ class D_FlipFlop : public Component {
protected:
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
};

#endif
25 changes: 25 additions & 0 deletions qucs/components/dff_SR.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#include "dff_SR.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"

dff_SR::dff_SR()
{
Expand All @@ -37,6 +38,7 @@ dff_SR::dff_SR()
ty = y2 + 4;
Model = "dff_SR";
Name = "Y";
SpiceModel = "A";
}

Component * dff_SR::newOne()
Expand Down Expand Up @@ -173,3 +175,26 @@ QString dff_SR::verilogCode( int )
" end\n";
return l;
}

QString dff_SR::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");

QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("Delay")->Value);

QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
QString D = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);
QString QB = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name);
QString Q = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name);

s += " " + D + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;

s += " " + tmp_model + "\n";
s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
.arg(tmp_model).arg(td);
return s;
}
1 change: 1 addition & 0 deletions qucs/components/dff_SR.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ class dff_SR : public Component
void createSymbol();
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
};

#endif /* dff_SR_H */
26 changes: 26 additions & 0 deletions qucs/components/jkff_SR.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#include "jkff_SR.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"

jkff_SR::jkff_SR()
{
Expand All @@ -37,6 +38,7 @@ jkff_SR::jkff_SR()
ty = y2 + 4;
Model = "jkff_SR";
Name = "Y";
SpiceModel = "A";
}

Component * jkff_SR::newOne()
Expand Down Expand Up @@ -183,3 +185,27 @@ QString jkff_SR::verilogCode( int )
" end\n";
return l;
}

QString jkff_SR::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");

QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("Delay")->Value);

QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
QString J = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
QString K = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);
QString RESET = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name);
QString QB = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name);
QString Q = spicecompat::normalize_node_name(Ports.at(6)->Connection->Name);

s += " " + J + " " + K + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;

s += " " + tmp_model + "\n";
s += QString(".model %1 d_jkff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
.arg(tmp_model).arg(td);
return s;
}
1 change: 1 addition & 0 deletions qucs/components/jkff_SR.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ class jkff_SR : public Component
void createSymbol();
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
};

#endif /* jkff_SR_H */
27 changes: 26 additions & 1 deletion qucs/components/tff_SR.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#include "tff_SR.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"

tff_SR::tff_SR()
{
Expand All @@ -36,7 +37,8 @@ tff_SR::tff_SR()
tx = x1 + 4;
ty = y2 + 4;
Model = "tff_SR";
Name = "Y";
Name = "Y";
SpiceModel = "A";
}

Component * tff_SR::newOne()
Expand Down Expand Up @@ -174,3 +176,26 @@ QString tff_SR::verilogCode( int )
" end\n";
return l;
}

QString tff_SR::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");

QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("Delay")->Value);

QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
QString T = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);
QString QB = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name);
QString Q = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name);

s += " " + T + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;

s += " " + tmp_model + "\n";
s += QString(".model %1 d_tff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
.arg(tmp_model).arg(td);
return s;
}
1 change: 1 addition & 0 deletions qucs/components/tff_SR.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ class tff_SR : public Component
void createSymbol();
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
};

#endif /* tff_SR_H */
8 changes: 4 additions & 4 deletions qucs/module.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -447,11 +447,7 @@ void Module::registerModules (void) {
REGISTER_DIGITAL_1 (fa1b);
REGISTER_DIGITAL_1 (fa2b);
REGISTER_DIGITAL_1 (RS_FlipFlop);
REGISTER_DIGITAL_1 (D_FlipFlop);
REGISTER_DIGITAL_1 (dff_SR);
REGISTER_DIGITAL_1 (JK_FlipFlop);
REGISTER_DIGITAL_1 (jkff_SR);
REGISTER_DIGITAL_1 (tff_SR);
REGISTER_DIGITAL_1 (gatedDlatch);
REGISTER_DIGITAL_1 (logic_0);
REGISTER_DIGITAL_1 (logic_1);
Expand Down Expand Up @@ -481,6 +477,10 @@ void Module::registerModules (void) {
REGISTER_DIGITAL_1 (Logical_AND);
REGISTER_DIGITAL_1 (Logical_XOR);
REGISTER_DIGITAL_1 (Logical_XNOR);
REGISTER_DIGITAL_1 (D_FlipFlop);
REGISTER_DIGITAL_1 (dff_SR);
REGISTER_DIGITAL_1 (jkff_SR);
REGISTER_DIGITAL_1 (tff_SR);
}

// file components
Expand Down

0 comments on commit 7e2f2ab

Please sign in to comment.