RISC--V-Processor

In the RISC V processor, the term RISC stands for “reduced instruction set computer” which executes few computer instructions whereas ‘V’ stands for the 5th generation. It is an open-source hardware ISA (instruction set architecture) based on the established principle of RISC. To get a better understanding follow this link

Here we are going to design the process using RISC V

Problem Statement: Design an ALU to implement the below operations:

1. Addition
2. Substraction
3. Logical operations (OR, AND, XOR)
4. Comparison

Solution:

In this project we implement a 32-bit, RISC-V based processor in verilog. The sub-modules that are used and their interaction with each other are shown in the following picture. To get a clear picture, the logic behind this processor please follow this wikipage

Waveform:

Tool used:

EDA playground