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rakshitharnayak/README.md 

"user creativity";
import { Person } from 'India';

new Person({
    name   : 'Rakshitha R Nayak',
    title  : 'Verification Engineer',
    email  : 'rakshitharnayak13@gmail.com'
}).introduce();
D:\Rakshitha R Nayak> node index.js
Hi, my name is Rakshitha R Nayak, I'm a Verification Engineer.

    🧑‍💻Frequently Used Tech🧑‍💻

🌐 Socials:

LinkedIn

📊 GitHub Stats:



Pinned

  1. axi4_testbench axi4_testbench Public

    Forked from axyrai/axi4_testbench

    SystemVerilog 1

  2. DRAM_VERIFICATION DRAM_VERIFICATION Public

    JavaScript

  3. Synchronous_FIFO Synchronous_FIFO Public

    A synchronous FIFO refers to a FIFO design where data values are written sequentially into a memory array using a clock signal, and the data values are sequentially read out from the memory array u…

    SystemVerilog

  4. RISC--V-Processor RISC--V-Processor Public

    RISC V PROCESSOR DESIGN IN VERILOG

    Verilog

  5. RAL_MODEL RAL_MODEL Public

    SystemVerilog

  6. SOLVESUDOKU SOLVESUDOKU Public

    SOLVE SUDOKU IN SYSTEM VERILOG

    SystemVerilog