Add workaround to IPF emulation bug to allow libdragon to boot

src/n64.rs

@@ -16,12 +16,12 @@ use std::path::Path;
 
 use super::ai::Ai;
 use super::cartridge::{Cartridge, CicModel};
-use super::r4300::R4300;
 use super::dp::Dp;
 use super::errors::*;
 use super::mi::Mi;
 use super::mips64;
 use super::pi::Pi;
+use super::r4300::R4300;
 use super::ri::Ri;
 use super::si::Si;
 use super::sp::{Sp, RSPCPU};
@@ -181,6 +181,13 @@ impl N64 {
         }
 
         R4300::get_mut().bus.write::<u32>(0x1FC0_07E4, seed);
+
+        // FIXME: fix RDRAM initialization emulation. IPL3 does initialize RDRAM (starting at 0x0400_0040),
+        // and is supposed to end up writing the RAM size at 0x8000_0318, but it does not currently work.
+        // This is relied upon by libdragon at least. So fix it by setting the RDRAM as already initialized
+        // and copying the RAM size.
+        R4300::get_mut().bus.write::<u32>(0x0470_000C, 0x14);
+        R4300::get_mut().bus.write::<u32>(0x0000_0318, 4*1024*1024);
         Ok(())
     }
 }

src/ri.rs

@@ -17,7 +17,7 @@ pub struct Ri {
     #[reg(bank = 1, offset = 0x08)]
     reg_rdram_delay: Reg32,
 
-    #[reg(bank = 1, offset = 0x0C)]
+    #[reg(bank = 1, offset = 0x0C, readonly)]
     reg_rdram_mode: Reg32,
 
     #[reg(bank = 1, offset = 0x10)]
@@ -41,12 +41,12 @@ pub struct Ri {
     // [1:0] operating mode
     // [2] stop T active
     // [3] stop R active
-    #[reg(bank = 2, offset = 0x00, init = 0xE, rwmask = 0xF)]
+    #[reg(bank = 2, offset = 0x00, rwmask = 0xF)]
     reg_ri_mode: Reg32,
 
     // [5:0] current control input
     // [6] current control enable
-    #[reg(bank = 2, offset = 0x04, init = 0x40, rwmask = 0x3F)]
+    #[reg(bank = 2, offset = 0x04, rwmask = 0x3F)]
     reg_ri_config: Reg32,
 
     // (W): [] any write updates current control register
@@ -55,15 +55,15 @@ pub struct Ri {
 
     // [2:0] receive select
     // [2:0] transmit select
-    #[reg(bank = 2, offset = 0x0C, init = 0x14, rwmask = 0xF)]
+    #[reg(bank = 2, offset = 0x0C, rwmask = 0xF)]
     reg_ri_select: Reg32,
 
     // [7:0] clean refresh delay
     // [15:8] dirty refresh delay
     // [16] refresh bank
     // [17] refresh enable
     // [18] refresh optimize
-    #[reg(bank = 2, offset = 0x10, init = 0x63634, rwmask = 0x7FFFF)]
+    #[reg(bank = 2, offset = 0x10, rwmask = 0x7FFFF)]
     reg_ri_refresh: Reg32,
 
     // [3:0] DMA latency/overlap