Merge pull request #143 from codelec/noautoclonetype

remove cloneType in favour of autoclonetype

src/main/scala/bpu/2bc-table.scala

@@ -46,7 +46,7 @@ import chisel3.util._
 import boom.util.SeqMem1rwTransformable
 
 
-class UpdateEntry(fetch_width: Int, index_sz: Int) extends Bundle
+class UpdateEntry(val fetch_width: Int, val index_sz: Int) extends Bundle
 {
    val index            = UInt(index_sz.W)
    val executed         = Vec(fetch_width, Bool())
@@ -57,17 +57,15 @@ class UpdateEntry(fetch_width: Int, index_sz: Int) extends Bundle
    // If takens(i), then we initialize entry to Weak-Taken. Otherwise, Weak-NotTaken.
    val do_initialize    = Bool()
 
-   override def cloneType: this.type = new UpdateEntry(fetch_width, index_sz).asInstanceOf[this.type]
 }
 
 
-class BrTableUpdate(fetch_width: Int, index_sz: Int) extends Bundle
+class BrTableUpdate(val fetch_width: Int, val index_sz: Int) extends Bundle
 {
    val index      = UInt(index_sz.W)
    val executed   = UInt(fetch_width.W) // which words in the fetch packet does the update correspond to?
    val new_value  = UInt(fetch_width.W)
 
-   override def cloneType: this.type = new BrTableUpdate(fetch_width, index_sz).asInstanceOf[this.type]
 }
 
 

src/main/scala/bpu/base-only.scala

@@ -74,6 +74,5 @@ class BaseOnlyBrPredictor(
 
    override def toString: String = "  Building no predictor (just using BIM as a base predictor)."
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 

src/main/scala/bpu/bim.scala

@@ -381,6 +381,5 @@ class BimodalTable(implicit p: Parameters) extends BoomModule()(p) with HasBimPa
       "\n   (" + size_kbits + " Kbits = " + size_kbits/8 + " kB) Bimodal Table (" +
       nSets + " entries across " + nBanks + " banks)"
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 

src/main/scala/bpu/brpredictor.scala

@@ -266,7 +266,6 @@ abstract class BrPredictor(
 
    //************************************************
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 
 

src/main/scala/bpu/btb.scala

@@ -183,7 +183,6 @@ abstract class BoomBTB(implicit p: Parameters) extends BoomModule()(p) with HasB
       val status_debug = Input(Bool())
    })
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 
 object BoomBTB

src/main/scala/bpu/dense-btb.scala

@@ -410,5 +410,4 @@ class DenseBTB(implicit p: Parameters) extends BoomBTB
       "\n   Offset Size   : " + offset_sz + "\n" +
       bim.toString
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }

src/main/scala/bpu/gshare.scala

@@ -44,7 +44,7 @@ trait HasGShareParameters extends HasBoomCoreParameters
 }
 
 
-class GShareResp(fetch_width: Int, idx_sz: Int) extends Bundle
+class GShareResp(val fetch_width: Int, val idx_sz: Int) extends Bundle
 {
    val debug_index = UInt(idx_sz.W) // Can recompute index during update (but let's check for errors).
    val rowdata = UInt((fetch_width*2).W) // Store to prevent a re-read during an update.
@@ -62,7 +62,6 @@ class GShareResp(fetch_width: Int, idx_sz: Int) extends Bundle
       cntr
    }
 
-   override def cloneType: this.type = new GShareResp(fetch_width, idx_sz).asInstanceOf[this.type]
 }
 
 object GShareBrPredictor

src/main/scala/bpu/tage-table.scala

@@ -19,11 +19,11 @@ import freechips.rocketchip.util.Str
 import boom.common._
 
 class TageTableIo(
-   fetch_width: Int,
-   index_sz: Int,
-   tag_sz: Int,
-   cntr_sz: Int,
-   ubit_sz: Int)
+   val fetch_width: Int,
+   val index_sz: Int,
+   val tag_sz: Int,
+   val cntr_sz: Int,
+   val ubit_sz: Int)
    extends Bundle
 {
    // bp1 - request a prediction (provide the index and tag).
@@ -63,19 +63,16 @@ class TageTableIo(
 
    val do_reset = Input(Bool())
 
-   override def cloneType: this.type = new TageTableIo(
-      fetch_width, index_sz, tag_sz, cntr_sz, ubit_sz).asInstanceOf[this.type]
 }
 
-class TageTableReq(index_sz: Int, tag_sz: Int) extends Bundle
+class TageTableReq(val index_sz: Int, val tag_sz: Int) extends Bundle
 {
    val index = UInt(index_sz.W)
    val tag = UInt(tag_sz.W)
 
-   override def cloneType: this.type = new TageTableReq(index_sz, tag_sz).asInstanceOf[this.type]
 }
 
-class TageTableResp(fetch_width: Int, tag_sz: Int, cntr_sz: Int, ubit_sz: Int) extends Bundle
+class TageTableResp(val fetch_width: Int, val tag_sz: Int, val cntr_sz: Int, val ubit_sz: Int) extends Bundle
 {
    val tag  = UInt(tag_sz.W)
    val cntr = UInt(cntr_sz.W)
@@ -84,20 +81,18 @@ class TageTableResp(fetch_width: Int, tag_sz: Int, cntr_sz: Int, ubit_sz: Int) e
 
    def predictsTaken = cntr(cntr_sz-1)
 
-   override def cloneType: this.type = new TageTableResp(fetch_width, tag_sz, cntr_sz, ubit_sz).asInstanceOf[this.type]
 }
 
-class TageTableEntry(fetch_width: Int, tag_sz: Int, cntr_sz: Int, ubit_sz: Int) extends Bundle
+class TageTableEntry(val fetch_width: Int, val tag_sz: Int, val cntr_sz: Int, val ubit_sz: Int) extends Bundle
 {
    val tag  = UInt(tag_sz.W)                 // Tag.
    val cntr = UInt(cntr_sz.W)                // Prediction counter.
    val cidx = UInt(log2Ceil(fetch_width).W)  // Control-flow instruction index.
    val ubit = UInt(ubit_sz.W)                // Usefulness counter.
 
-   override def cloneType: this.type = new TageTableEntry(fetch_width, tag_sz, cntr_sz, ubit_sz).asInstanceOf[this.type]
 }
 
-class TageTableWrite(fetch_width: Int, index_sz: Int, tag_sz: Int, cntr_sz: Int, ubit_sz: Int) extends Bundle
+class TageTableWrite(val fetch_width: Int, val index_sz: Int, val tag_sz: Int, val cntr_sz: Int, val ubit_sz: Int) extends Bundle
 {
    val index = UInt(index_sz.W)
    val old = new TageTableEntry(fetch_width, tag_sz, cntr_sz, ubit_sz)
@@ -110,8 +105,6 @@ class TageTableWrite(fetch_width: Int, index_sz: Int, tag_sz: Int, cntr_sz: Int,
    val mispredict = Bool()
    val taken = Bool()
 
-   override def cloneType: this.type = new TageTableWrite(fetch_width, index_sz, tag_sz, cntr_sz,
-                                                          ubit_sz).asInstanceOf[this.type]
 }
 
 
@@ -269,6 +262,5 @@ class TageTable(
       tag_sz + "-bit tags, " +
       cntr_sz + "-bit counters"
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 

src/main/scala/bpu/tage.scala

@@ -45,13 +45,13 @@ case class TageParameters(
    ubit_sz: Int = 1)
 
 class TageResp(
-   fetch_width: Int,
-   num_tables: Int,
-   max_history_length: Int,
-   max_index_sz: Int,
-   max_tag_sz: Int,
-   cntr_sz: Int,
-   ubit_sz: Int
+   val fetch_width: Int,
+   val num_tables: Int,
+   val max_history_length: Int,
+   val max_index_sz: Int,
+   val max_tag_sz: Int,
+   val cntr_sz: Int,
+   val ubit_sz: Int
    )
    extends Bundle
 {
@@ -75,15 +75,6 @@ class TageResp(
    val debug_indexes  = Vec(num_tables, UInt(max_index_sz.W))
    val debug_tags     = Vec(num_tables, UInt(max_tag_sz.W))
 
-   override def cloneType: this.type =
-      new TageResp(
-         fetch_width,
-         num_tables,
-         max_history_length,
-         max_index_sz,
-         max_tag_sz,
-         cntr_sz,
-         ubit_sz).asInstanceOf[this.type]
 }
 
 // provide information to the BpdResp bundle how many bits a TageResp needs
@@ -500,6 +491,5 @@ class TageBrPredictor(
       (size_in_bits/1024) + " Kbits) (max history length: " + history_lengths.max + " bits)\n" +
       tables.mkString("\n")
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 

src/main/scala/common/microop.scala

@@ -168,9 +168,8 @@ object CfiType
    def jalr = 3.U
 }
 
-class MicroOpWithData(data_sz: Int)(implicit p: Parameters) extends BoomBundle()(p)
+class MicroOpWithData(val data_sz: Int)(implicit p: Parameters) extends BoomBundle()(p)
   with HasBoomUOP
 {
    val data = UInt(data_sz.W)
-   override def cloneType = new MicroOpWithData(data_sz)(p).asInstanceOf[this.type]
 }

src/main/scala/exu/core.scala

@@ -1557,6 +1557,5 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    }
 
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 

src/main/scala/exu/decode.scala

@@ -352,7 +352,6 @@ class DecodeUnitIo(implicit p: Parameters) extends BoomBundle()(p)
    val interrupt = Input(Bool())
    val interrupt_cause = Input(UInt(xLen.W))
 
-   override def cloneType: this.type = new DecodeUnitIo()(p).asInstanceOf[this.type]
 }
 
 // Takes in a single instruction, generates a MicroOp.
@@ -466,7 +465,6 @@ class DecodeUnit(implicit p: Parameters) extends BoomModule()(p)
 
    //-------------------------------------------------------------
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 
 
@@ -601,6 +599,5 @@ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) exten
 
    io.debug.branch_mask := branch_mask
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 

src/main/scala/exu/execute.scala

@@ -29,14 +29,13 @@ import boom.ifu.GetPCFromFtqIO
 import boom.util.{ImmGen, IsKilledByBranch, BranchKillableQueue}
 
 // TODO rename to something like MicroOpWithData
-class ExeUnitResp(data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
+class ExeUnitResp(val data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
   with HasBoomUOP
 {
    val data = Bits(data_width.W)
    val fflags = new ValidIO(new FFlagsResp) // write fflags to ROB
 
    var writesToIRF = true // does this response unit plug into the integer regfile?
-   override def cloneType: this.type = new ExeUnitResp(data_width).asInstanceOf[this.type]
 }
 
 class FFlagsResp(implicit p: Parameters) extends BoomBundle()(p)

src/main/scala/exu/fppipeline.scala

@@ -322,5 +322,4 @@ class FpPipeline(implicit p: Parameters) extends BoomModule()(p) with tile.HasFP
       "\n   Num Wakeup Ports      : " + num_wakeup_ports +
       "\n   Num Bypass Ports      : " + exe_units.num_total_bypass_ports + "\n"
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }

src/main/scala/exu/functional_unit.scala

@@ -93,7 +93,7 @@ class GetPredictionInfo(implicit p: Parameters) extends BoomBundle()(p)
    val info = Input(new BranchPredInfo())
 }
 
-class FuncUnitReq(data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
+class FuncUnitReq(val data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
   with HasBoomUOP
 {
    val num_operands = 3
@@ -104,10 +104,9 @@ class FuncUnitReq(data_width: Int)(implicit p: Parameters) extends BoomBundle()(
 
    val kill = Bool() // kill everything
 
-   override def cloneType = new FuncUnitReq(data_width)(p).asInstanceOf[this.type]
 }
 
-class FuncUnitResp(data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
+class FuncUnitResp(val data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
   with HasBoomUOP
 {
    val data = UInt(data_width.W)
@@ -116,17 +115,15 @@ class FuncUnitResp(data_width: Int)(implicit p: Parameters) extends BoomBundle()
    val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU
    val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc
 
-   override def cloneType = new FuncUnitResp(data_width)(p).asInstanceOf[this.type]
 }
 
-class BypassData(num_bypass_ports: Int, data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
+class BypassData(val num_bypass_ports: Int, val data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
 {
    val valid = Vec(num_bypass_ports, Bool())
    val uop   = Vec(num_bypass_ports, new MicroOp())
    val data  = Vec(num_bypass_ports, UInt(data_width.W))
 
    def getNumPorts: Int = num_bypass_ports
-   override def cloneType: this.type = new BypassData(num_bypass_ports, data_width).asInstanceOf[this.type]
 }
 
 class BrResolutionInfo(implicit p: Parameters) extends BoomBundle()(p)

src/main/scala/exu/issue.scala

@@ -175,7 +175,6 @@ abstract class IssueUnit(
       else if (iqType == IQT_FP.litValue) " fp"
       else "unknown"
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 
 class IssueUnits(num_wakeup_ports: Int)(implicit val p: Parameters)

src/main/scala/exu/issue_slot.scala

@@ -24,7 +24,7 @@ import freechips.rocketchip.config.Parameters
 import boom.common._
 import boom.util._
 
-class IssueSlotIO(num_wakeup_ports: Int)(implicit p: Parameters) extends BoomBundle()(p)
+class IssueSlotIO(val num_wakeup_ports: Int)(implicit p: Parameters) extends BoomBundle()(p)
 {
    val valid          = Output(Bool())
    val will_be_valid  = Output(Bool()) // TODO code review, do we need this signal so explicitely?
@@ -53,7 +53,6 @@ class IssueSlotIO(num_wakeup_ports: Int)(implicit p: Parameters) extends BoomBun
     Output(result)
   }
 
-   override def cloneType = new IssueSlotIO(num_wakeup_ports)(p).asInstanceOf[this.type]
 }
 
 class IssueSlot(num_slow_wakeup_ports: Int)(implicit p: Parameters)
@@ -318,6 +317,5 @@ class IssueSlot(num_slow_wakeup_ports: Int)(implicit p: Parameters)
    io.debug.p3 := slot_p3
    io.debug.state := slot_state
 
-   override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
 }
 

src/main/scala/exu/regfile.scala

@@ -18,18 +18,16 @@ import freechips.rocketchip.config.Parameters
 import scala.collection.mutable.ArrayBuffer
 import boom.common._
 
-class RegisterFileReadPortIO(addr_width: Int, data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
+class RegisterFileReadPortIO(val addr_width: Int, val data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
 {
    val addr = Input(UInt(addr_width.W))
    val data = Output(UInt(data_width.W))
-   override def cloneType = new RegisterFileReadPortIO(addr_width, data_width)(p).asInstanceOf[this.type]
 }
 
-class RegisterFileWritePort(addr_width: Int, data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
+class RegisterFileWritePort(val addr_width: Int, val data_width: Int)(implicit p: Parameters) extends BoomBundle()(p)
 {
    val addr = UInt(width = addr_width.W)
    val data = UInt(width = data_width.W)
-   override def cloneType = new RegisterFileWritePort(addr_width, data_width)(p).asInstanceOf[this.type]
 }
 
 

src/main/scala/exu/registerread.scala

@@ -23,10 +23,10 @@ import boom.common._
 import boom.util._
 
 class RegisterReadIO(
-   issue_width: Int,
-   num_total_read_ports: Int,
-   num_total_bypass_ports: Int,
-   register_width: Int
+   val issue_width: Int,
+   val num_total_read_ports: Int,
+   val num_total_bypass_ports: Int,
+   val register_width: Int
 )(implicit p: Parameters) extends  BoomBundle()(p)
 {
    // issued micro-ops
@@ -44,9 +44,6 @@ class RegisterReadIO(
    val kill   = Input(Bool())
    val brinfo = Input(new BrResolutionInfo())
 
-   override def cloneType =
-      new RegisterReadIO(issue_width, num_total_read_ports, num_total_bypass_ports, register_width
-   )(p).asInstanceOf[this.type]
 }
 
 

src/main/scala/exu/rename-freelist.scala

@@ -60,11 +60,10 @@ class FreeListIo(
    val debug = Output(new DebugFreeListIO(num_phys_registers))
 }
 
-class DebugFreeListIO(num_phys_registers: Int) extends Bundle
+class DebugFreeListIO(val num_phys_registers: Int) extends Bundle
 {
    val freelist = Bits(num_phys_registers.W)
    val isprlist = Bits(num_phys_registers.W)
-   override def cloneType: this.type = new DebugFreeListIO(num_phys_registers).asInstanceOf[this.type]
 }
 
 // provide a fixed set of renamed destination registers